Paul Chow

Ruediger Willenberg, Paul Chow: A remote memory access infrastructure for global address space programming models in FPGAs. FPGA 2013: 211-220

Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow: Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms. Int. J. Reconfig. Comp. 2012 (2012)

Vincent Mirian, Paul Chow: FCache: a system for cache coherent processing on FPGAs. FPGA 2012: 233-236

S. Alexander Chin, Paul Chow: OpenCL memory infrastructure for FPGAs (abstract only). FPGA 2012: 269-270

Zhongduo Lin, Charles Lo, Paul Chow: K-means implementation on FPGA for high-dimensional data using triangle inequality. FPL 2012: 437-442

Vincent Mirian, Paul Chow: Managing mutex variables in a cache-coherent shared-memory system for FPGAs. FPT 2012: 43-46

Charles Lo, Paul Chow: A high-performance architecture for training Viola-Jones object detectors. FPT 2012: 174-181

Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei: Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method. FPT 2012: 190-197

Ruediger Willenberg, Paul Chow: SimXMD: Integrated debugging of C code and hardware components. FPT 2012: 309-312

Vincent Mirian, Paul Chow: An implementation of a directory protocol for a cache coherent system on FPGAs. ReConFig 2012: 1-6

Alexander Kaganov, Asif Lakhany, Paul Chow: FPGA Acceleration of MultiFactor CDO Pricing. TRETS 4(2): 20 (2011)

Lesley Shannon, Paul Chow: Leveraging reconfigurability in the hardware/software codesign process. TRETS 4(3): 28 (2011)

Charles Lo, Paul Chow: Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI. FPGA 2011: 189-198

Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang: Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. FPL 2011: 110-115

Yuanxi Peng, Manuel Saldaña, Paul Chow: Hardware Support for Broadcast and Reduce in MPSoC. FPL 2011: 144-150

Paul Chow, Michael J. Wirthlin (Eds.): IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011. IEEE Computer Society 2011

Daniel Le Ly, Paul Chow: High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines. IEEE Transactions on Neural Networks 21(11): 1780-1792 (2010)

Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Paul Chow, Ralph Wittig, Henry Styles, Andrew Putnam: MPI as a Programming Model for High-Performance Reconfigurable Computers. TRETS 3(4): 22 (2010)

Andrew W. H. House, Manuel Saldaña, Paul Chow: Integrating High-Level Synthesis into MPI. FCCM 2010: 175-178

Dharmendra P. Gupta, Paul Chow: Acceleration of an analytical approach to collateralized debt obligation pricing. FPGA 2010: 103-106

Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow: Using Partial Reconfiguration in an Embedded Message-Passing System. ReConFig 2010: 418-423

Hadi Bannazadeh, Alberto Leon-Garcia, Keith Redmond, G. Tam, A. Khan, M. Ma, S. Dani, Paul Chow: Virtualized Application Networking Infrastructure. TRIDENTCOM 2010: 363-382

Manuel Saldaña, Emanuel Ramalho, Paul Chow: A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems. Int. J. Reconfig. Comp. 2009 (2009)

Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose: FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. FCCM 2009: 157-164

Daniel Le Ly, Paul Chow: A high-performance FPGA architecture for restricted boltzmann machines. FPGA 2009: 73-82

Daniel Le Ly, Paul Chow: A multi-FPGA architecture for stochastic Restricted Boltzmann Machines. FPL 2009: 168-173

Daniel Le Ly, Manuel Saldaña, Paul Chow: The challenges of using an embedded MPI for hardware-based processing nodes. FPT 2009: 120-127

Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing: Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. ReConFig 2009: 48-53

Paul Chow, Peter Y. K. Cheung (Eds.): Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009. ACM 2009, isbn 978-1-60558-410-2

Tor M. Aamodt, Paul Chow: Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy. ACM Trans. Embedded Comput. Syst. 7(3) (2008)

Andrew W. H. House, Paul Chow: Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems. FCCM 2008: 291-292

Alexander Kaganov, Paul Chow, Asif Lakhany: FPGA acceleration of Monte-Carlo based credit derivative pricing. FPL 2008: 329-334

Daniel Nunes, Manuel Saldaña, Paul Chow: A profiler for a heterogeneous multi-core multi-FPGA system. FPT 2008: 113-120

Manuel Saldaña, Emanuel Ramalho, Paul Chow: A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI. ReConFig 2008: 265-270

Mike Hutton, Paul Chow (Eds.): Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008. ACM 2008, isbn 978-1-59593-934-0

Lesley Shannon, Paul Chow: SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. IEEE Trans. VLSI Syst. 15(4): 377-390 (2007)

Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow: Routability of Network Topologies in FPGAs. IEEE Trans. VLSI Syst. 15(8): 948-951 (2007)

Sam Lee, Paul Chow: An FPGA Implementation of Reciprocal Sums for SPME. ERSA 2007: 159-165

Paul Chow, Mike Hutton: Integrating FPGAs in high-performance computing: introduction. FPGA 2007: 131

Chichyang Chen, Paul Chow: Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor. ACM Great Lakes Symposium on VLSI 2007: 540-545

Tor M. Aamodt, Paul Chow: Optimization of data prefetch helper threads with path-expression based statistical modeling. ICS 2007: 210-221

Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Regis Pomes, Paul Chow: A Scalable FPGA-based Multiprocessor. FCCM 2006: 111-120

Manuel Saldaña, Lesley Shannon, Paul Chow: The routability of multiprocessor network topologies in FPGAs. FPGA 2006: 232

Manuel Saldaña, Paul Chow: TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. FPL 2006: 1-6

Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow: A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. FPL 2006: 1-6

Manuel Saldaña, Daniel Nunes, Emanuel Ramalho, Paul Chow: Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI. ReConFig 2006: 260-279

Manuel Saldaña, Lesley Shannon, Paul Chow: The routability of multiprocessor network topologies in FPGAs. SLIP 2006: 49-56

Lesley Shannon, Paul Chow: Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. FCCM 2005: 63-72

Lesley Shannon, Paul Chow: Leveraging Reconfigurability in the Design Process. FPL 2005: 731-732

Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow: Designing an FPGA SoC Using a Standardized IP Block Interface. FPT 2005: 341-342

Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow: Reconfigurable Molecular Dynamics Simulator. FCCM 2004: 197-206

Lesley Shannon, Paul Chow: Using reconfigurability to achieve real-time profiling for hardware/software codesign. FPGA 2004: 190-199

Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow: FPGA-based supercomputing: an implementation for molecular dynamics. FPGA 2004: 253

Lesley Shannon, Paul Chow: Maximizing system performance: using reconfigurability to monitor system communications. FPT 2004: 231-238

Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen: Hardware Support for Prescient Instruction Prefetch. HPCA 2004: 84-95

Lesley Shannon, Paul Chow: Standardizing the Performance Assessment of Reconfigurable Processor Architectures. FCCM 2003: 282-283

Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen: A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS 2003: 13-24

Jorge E. Carrillo, Paul Chow: The effect of reconfigurable units in superscalar processors. FPGA 2001: 141-150

L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia: A Scheduler ASIC for a Programmable Packet Switch. IEEE Micro 20(1): 42-48 (2000)

Tor M. Aamodt, Paul Chow: Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. CASES 2000: 128-137

Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. International Journal of Parallel Programming 27(5): 327-356 (1999)

Ivan Hamer, Paul Chow: DES Cracking on the Transmogrifier 2a. CHES 1999: 13-24

Jeffrey A. Jacob, Paul Chow: Memory Interfacing and Instruction Specification for Reconfigurable Processors. FPGA 1999: 145-154

David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. VLSI Syst. 6(2): 188-198 (1998)

David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA 1997: 53-61

Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA 1997: 133-143

Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO 1997: 149-159

Mazen A. R. Saghir, Paul Chow, Corinna G. Lee: Exploiting Dual Data-Memory Banks in Digital Signal Processors. ASPLOS 1996: 234-243

Keith I. Farkas, Norman P. Jouppi, Paul Chow: Register File Design Considerations in Dynamically Scheduled Processors. HPCA 1996: 40-51

Paul Chow, P. Glenn Gulak: A Field-Programmable Mixed-Analog-Digital Array. FPGA 1995: 104-109

Keith I. Farkas, Norman P. Jouppi, Paul Chow: How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? HPCA 1995: 78-89

Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manage. 30(6): 805-816 (1994)

Gennady Feygin, P. Glenn Gulak, Paul Chow: Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference 1994: 254-263

Gennady Feygin, Patrick Glenn Gulak, Paul Chow: A multiprocessor architecture for Viterbi decoders with linear speedup. IEEE Transactions on Signal Processing 41(9): 2907-2917 (1993)

Gennady Feygin, P. Glenn Gulak, Paul Chow: Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference 1993: 118-127

Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton: A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948

Paul Chow, Mark Horowitz: Architectural Tradeoffs in the Design of MIPS-X. ISCA 1987: 300-308

Paul Chow, Zvonko G. Vranesic, Jui Lin Yen: A Pipelined Distributed Arithmetic PFFT Processor. IEEE Trans. Computers 32(12): 1128-1136 (1983)