Chris Chu, Chris Chong-Nuen Chu
List of publications from the DBLP Bibliography Server - FAQ
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 | 2013 | |
|---|---|---|
| j31 |      | Jackey Z. Yan, Chris Chu: SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 32(2): 175-188 (2013) |
| 2012 | ||
| j30 | | Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang: Pad Assignment for Die-Stacking System-in-Package Design. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1711-1722 (2012) |
| j29 | | Wai-Kei Mak, Chris Chu: Rethinking the Wirelength Benefit of 3-D Integration. IEEE Trans. VLSI Syst. 20(12): 2346-2351 (2012) |
| j28 | | Min Pan, Yue Xu, Yanheng Zhang, Chris Chu: FastRoute: An Efficient and High-Quality Global Router. VLSI Design 2012 (2012) |
| j27 | | Xin Zhao, Chris Chu: Line Search-Based Inverse Lithography Technique for Mask Design. VLSI Design 2012 (2012) |
| c56 | | Yanheng Zhang, Chris Chu: GDRouter: interleaved global routing and detailed routing for ultimate routability. DAC 2012: 597-602 |
| c55 | | Jackey Z. Yan, Chris Chu: Optimal slack-driven block shaping algorithm in fixed-outline floorplanning. ISPD 2012: 179-186 |
| 2011 | ||
| j26 | | Gaurav Ajwani, Chris Chu, Wai-Kei Mak: FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 194-204 (2011) |
| j25 | | Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak: SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 1020-1033 (2011) |
| c54 | | |
| c53 | | Yanheng Zhang, Chris Chu: RegularRoute: an efficient detailed router with regular routing patterns. ISPD 2011: 45-52 |
| 2010 | ||
| j24 | | Jackey Z. Yan, Chris Chu: DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 367-381 (2010) |
| c52 | | Yue Xu, Chris Chu: An auction based pre-processing technique to determine detour in global routing. ICCAD 2010: 305-311 |
| c51 | | Gaurav Ajwani, Chris Chu, Wai-Kei Mak: FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. ISPD 2010: 27-34 |
| c50 | | Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu: ITOP: integrating timing optimization within placement. ISPD 2010: 83-90 |
| c49 | | |
| c48 | | Jackey Z. Yan, Chris Chu, Wai-Kei Mak: SafeChoice: a novel clustering algorithm for wirelength-driven placement. ISPD 2010: 185-192 |
| 2009 | ||
| j23 | | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu: Handling routability in floorplan design with twin binary trees. Integration 42(4): 449-456 (2009) |
| c47 | | Yue Xu, Yanheng Zhang, Chris Chu: FastRoute 4.0: global router with efficient via minimization. ASP-DAC 2009: 576-581 |
| c46 | | Jackey Z. Yan, Natarajan Viswanathan, Chris Chu: Handling complexities in modern large-scale mixed-size placement. DAC 2009: 436-441 |
| c45 | | Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang: Pad assignment for die-stacking System-in-Package design. ICCAD 2009: 249-255 |
| c44 | | Yanheng Zhang, Chris Chu: CROP: Fast and effective congestion refinement of placement. ICCAD 2009: 344-350 |
| c43 | | Yue Xu, Chris Chu: GREMA: Graph reduction based efficient mask assignment for double patterning technology. ICCAD 2009: 601-606 |
| 2008 | ||
| j22 | | Chris C. N. Chu, Yiu-Chung Wong: FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 70-83 (2008) |
| c42 | | Jackey Z. Yan, Chris Chu: DeFer: deferred decision making enabled fixed-outline floorplanner. DAC 2008: 161-166 |
| c41 | | Yanheng Zhang, Yue Xu, Chris Chu: FastRoute3.0: a fast and high quality global router based on virtual capacity. ICCAD 2008: 344-349 |
| r1 | | |
| 2007 | ||
| j21 | | Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu: Wire Retiming Problem With Net Topology Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1648-1660 (2007) |
| c40 | | Natarajan Viswanathan, Min Pan, Chris C. N. Chu: FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. ASP-DAC 2007: 135-140 |
| c39 | | Min Pan, Chris C. N. Chu, Priyadarshan Patra: A Novel Performance-Driven Topology Design Algorithm. ASP-DAC 2007: 244-249 |
| c38 | | Min Pan, Chris C. N. Chu: FastRoute 2.0: A High-quality and Efficient Global Router. ASP-DAC 2007: 250-255 |
| c37 | | |
| c36 | | Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu: RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC 2007: 453-458 |
| c35 | | Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia: The coming of age of physical synthesis. ICCAD 2007: 246-249 |
| 2006 | ||
| c34 | | Natarajan Viswanathan, Min Pan, Chris C. N. Chu: FastPlace 2.0: an efficient analytical placer for mixed-mode designs. ASP-DAC 2006: 195-200 |
| c33 | | Chiu-Wing Sham, Evangeline F. Y. Young, Chris C. N. Chu: Optimal cell flipping in placement and floorplanning. DAC 2006: 1109-1114 |
| c32 | | Chuan Lin, Hai Zhou, Chris C. N. Chu: A revisit to floorplan optimization by Lagrangian relaxation. ICCAD 2006: 164-171 |
| c31 | | Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu: Analog placement with symmetry and other placement constraints. ICCAD 2006: 349-354 |
| c30 | | Min Pan, Chris C. N. Chu: FastRoute: a step to integrate global routing into placement. ICCAD 2006: 464-471 |
| c29 | | Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu: Post-placement voltage island generation. ICCAD 2006: 641-646 |
| 2005 | ||
| j20 | | Sampath Dechu, Zion Cien Shen, Chris C. N. Chu: An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 600-608 (2005) |
| j19 | | Natarajan Viswanathan, Chris C. N. Chu: FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 722-733 (2005) |
| c28 |  | Min Pan, Natarajan Viswanathan, Chris C. N. Chu: An efficient and effective detailed placement algorithm. ICCAD 2005: 48-55 |
| c27 | | Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li: Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. ICCD 2005: 38-44 |
| c26 | | Min Pan, Chris C. N. Chu, J. Morris Chang: Transition time bounded low-power clock tree construction. ISCAS (3) 2005: 2445-2448 |
| c25 | | Min Pan, Chris C. N. Chu, Hai Zhou: Timing yield estimation using statistical static timing analysis. ISCAS (3) 2005: 2461-2464 |
| c24 | | Chris C. N. Chu, Yiu-Chung Wong: Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. ISPD 2005: 28-35 |
| c23 | | Natarajan Viswanathan, Min Pan, Chris C. N. Chu: FastPlace: an analytical placer for mixed-mode designs. ISPD 2005: 221-223 |
| 2004 | ||
| j18 | | Chris C. N. Chu, Evangeline F. Y. Young: Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 71-79 (2004) |
| j17 | | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004) |
| j16 | | Arif Ishaq Abou-Seido, Brian Nowak, Chris Chong-Nuen Chu: Fitted Elmore delay: a simple and accurate interconnect delay model. IEEE Trans. VLSI Syst. 12(7): 691-696 (2004) |
| j15 | | Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho: Placement constraints in floorplan design. IEEE Trans. VLSI Syst. 12(7): 735-745 (2004) |
| c22 | | Sampath Dechu, Zion Cien Shen, Chris C. N. Chu: An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. ASP-DAC 2004: 361-366 |
| c21 | | Zion Cien Shen, Chris C. N. Chu: Accurate and efficient flow based congestion estimation in floorplanning. ASP-DAC 2004: 671-676 |
| c20 | | |
| c19 | | Natarajan Viswanathan, Chris C. N. Chu: FastPlace: efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. ISPD 2004: 26-33 |
| c18 | | Debjit Sinha, Hai Zhou, Chris C. N. Chu: Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181 |
| 2003 | ||
| j14 | | Daniel Berleant, Mei-Peng Cheong, Chris C. N. Chu, Yong Guan, Ahmed E. Kamal, Gerald Shedblé, Scott Ferson, James F. Peters: Dependable Handling of Uncertainty. Reliable Computing 9(6): 407-418 (2003) |
| j13 | | Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen: Twin binary sequences: a nonredundant representation for general nonslicing floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 457-469 (2003) |
| j12 | | Zion Cien Shen, Chris C. N. Chu: Bounds on the number of slicing, mosaic, and general floorplans. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1354-1361 (2003) |
| c17 | | Steve T. W. Lai, Evangeline F. Y. Young, Chris C. N. Chu: A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees. DATE 2003: 10856-10861 |
| c16 | | Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu: Retiming with Interconnect and Gate Delay. ICCAD 2003: 221-226 |
| c15 | | Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz: Optimizing SOC Test Resources using Dual Sequences. VLSI-SOC 2003: 180-185 |
| 2002 | ||
| c14 | | Chris C. N. Chu, Evangeline F. Y. Young: Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design. DATE 2002: 1101 |
| c13 | | Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Chu: Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. ICCD 2002: 422-427 |
| c12 | | Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109 |
| c11 | | Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen: Twin binary sequences: a non-redundant representation for general non-slicing floorplan. ISPD 2002: 196-201 |
| c10 | | Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho: A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. VLSI Design 2002: 661- |
| 2001 | ||
| j11 | | Chris C. N. Chu, D. F. Wong: VLSI Circuit Performance Optimization by Geometric Programming. Annals OR 105(1-4): 37-60 (2001) |
| j10 | | Yu-Yen Mo, Chris C. N. Chu: Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 680-686 (2001) |
| j9 | | Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong: Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 687-692 (2001) |
| j8 | | Chris C. N. Chu, D. F. Wong: Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. 6(3): 343-371 (2001) |
| 2000 | ||
| c9 | | |
| c8 | | Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong: Floorplan area minimization using Lagrangian relaxation. ISPD 2000: 174-179 |
| 1999 | ||
| j7 | | Fung Yu Young, Chris C. N. Chu, D. F. Wong: Generation of Universal Series-Parallel Boolean Functions. J. ACM 46(3): 416-435 (1999) |
| j6 | | Chris C. N. Chu, Martin D. F. Wong: Greedy wire-sizing is linear time. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 398-405 (1999) |
| j5 | | Chris C. N. Chu, Martin D. F. Wong: A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 787-798 (1999) |
| j4 | | Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1014-1025 (1999) |
| j3 | | Chris C. N. Chu, Martin D. F. Wong: An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1297-1304 (1999) |
| 1998 | ||
| j2 | | Chris C. N. Chu, Martin D. F. Wong: A matrix synthesis approach to thermal placement. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1166-1174 (1998) |
| c7 | | Chris C. N. Chu, D. F. Wong: A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE 1998: 479-485 |
| c6 | | Chung-Ping Chen, Chris C. N. Chu, D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD 1998: 617-624 |
| c5 | | |
| 1997 | ||
| c4 | | Chris C. N. Chu, D. F. Wong: A new approach to simultaneous buffer insertion and wire sizing. ICCAD 1997: 614-621 |
| c3 | | |
| c2 | | Chris C. N. Chu, D. F. Wong: Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD 1997: 192-197 |
| 1996 | ||
| j1 | | Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wei-Kei Mak: Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. J. Parallel Distrib. Comput. 33(1): 98-106 (1996) |
| 1993 | ||
| c1 | | Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wai-Kei Mak: Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. SPDP 1993: 285-289 |
Colors in the list of coauthors
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