| 1998 | ||
|---|---|---|
| j1 | Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang: On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. VLSI Syst. 6(4): 634-642 (1998) | |
| 1 | Juinn-Dar Huang | |
| 2 | Jing-Yang Jou | |
| 3 | Wen-Zen Shen |
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