Jason Cong

Chunhua Xiao, M.-C. Frank Chang, Jason Cong, Michael Gill, Zhangqin Huang, Chunyue Liu, Glenn Reinman, Hao Wu: Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects. TACO 9(4): 60 (2013)

Guojie Luo, Yiyu Shi, Jason Cong: An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. IEEE Trans. on CAD of Integrated Circuits and Systems 32(4): 510-523 (2013)

Amit Agarwal, Jason Cong, Brian Tagiku: The survivability of design-specific spare placement in FPGA architectures with high defect rates. ACM Trans. Design Autom. Electr. Syst. 18(2): 33 (2013)

Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao: Optimizing routability in large-scale mixed-size placement. ASP-DAC 2013: 441-446

Wei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, Jason Cong: Improving high level synthesis optimization opportunity through polyhedral transformations. FPGA 2013: 9-18

Louis-Noël Pouchet, Peng Zhang, P. Sadayappan, Jason Cong: Polyhedral-based data reuse optimization for configurable computing. FPGA 2013: 29-38

Vaughn Betz, Jason Cong: Are FPGAs suffering from the innovator's dilemna? FPGA 2013: 135-136

Jason Cong, Karthik Gururaj: Architecture support for custom instructions with memory operations. FPGA 2013: 231-234

Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong: Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only). FPGA 2013: 269

Jason Cong, Muhuan Huang, Peng Zhang: Efficient system-level mapping from streaming applications to FPGAs (abstract only). FPGA 2013: 277

Jason Cong, Bingjun Xiao: Defect recovery in nanodevice-based programmable interconnects (abstract only). FPGA 2013: 277-278

Yanghyo Kim, Sai-Wang Tam, Gyungsu Byun, Hao Wu, Lan Nan, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang: Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 200-209 (2012)

Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang: Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 210-227 (2012)

Jianwen Chen, Jason Cong, Luminita A. Vese, John D. Villasenor, Ming Yan, Yi Zou: A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(3): 616-625 (2012)

Jason Cong, Karthik Gururaj, Peng Zhang, Yi Zou: Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections. J. Electrical and Computer Engineering 2012 (2012)

Kanit Therdsteerasukdi, Gyungsu Byun, Jason Cong, M. Frank Chang, Glenn Reinman: Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system. TACO 8(4): 51 (2012)

Alex A. T. Bui, Kwang-Ting Cheng, Jason Cong, Luminita A. Vese, Yi-Chu Wang, Bo Yuan, Yi Zou: Platform characterization for Domain-Specific Computing. ASP-DAC 2012: 94-99

Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong: An integrated and automated memory optimization flow for FPGA behavioral synthesis. ASP-DAC 2012: 257-262

Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar, Glenn Reinman, Marco Vitanza: Compilation and architecture support for customized vector instruction extension. ASP-DAC 2012: 652-657

Hao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewnpu Jou, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang: A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration. CICC 2012: 1-4

Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman: Architecture support for accelerator-rich CMPs. DAC 2012: 843-849

Jason Cong, Peng Zhang, Yi Zou: Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. DAC 2012: 1233-1238

Jason Cong, Bin Liu: A metric for layout-friendly microarchitecture optimization in high-level synthesis. DAC 2012: 1239-1244

Yu-Ting Chen, Jason Cong, Hui Huang, Bin Liu, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman: Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. DATE 2012: 45-50

Jason Cong, Muhuan Huang, Bin Liu, Peng Zhang, Yi Zou: Combining module selection and replication for throughput-driven streaming programs. DATE 2012: 1018-1023

Jianwen Chen, Jason Cong, Ming Yan, Yi Zou: FPGA-accelerated 3D reconstruction using compressive sensing. FPGA 2012: 163-166

Jason Cong, Bingjun Xiao: FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only). FPGA 2012: 268

Peng Li, Yuxin Wang, Peng Zhang, Guojie Luo, Tao Wang, Jason Cong: Memory partitioning and scheduling co-optimization in behavioral synthesis. ICCAD 2012: 488-495

Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman: BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs. ISLPED 2012: 225-230

Yu-Ting Chen, Jason Cong, Hui Huang, Chunyue Liu, Raghu Prabhakar, Glenn Reinman: Static and dynamic co-optimizations for blocks mapping in hybrid caches. ISLPED 2012: 237-242

Jason Cong, Bo Yuan: Energy-efficient scheduling on heterogeneous multi-core architectures. ISLPED 2012: 345-350

Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman: CHARM: a composable heterogeneous accelerator-rich microprocessor. ISLPED 2012: 379-384

Jason Cong: Transformation from ad hoc EDA to algorithmic EDA. ISPD 2012: 57-62

Jason Cong, Bin Liu, Guojie Luo, Raghu Prabhakar: Towards layout-friendly high-level synthesis. ISPD 2012: 165-172

Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong: Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. ISQED 2012: 129-136

Yanghyo Kim, Gyungsu Byun, Adrian Tang, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang: An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. ISSCC 2012: 50-52

Jason Cong, Bin Liu, Raghu Prabhakar, Peng Zhang: A Study on the Impact of Compiler Optimizations on High-Level Synthesis. LCPC 2012: 143-157

Alina Simion Sbîrlea, Yi Zou, Zoran Budimlic, Jason Cong, Vivek Sarkar: Mapping a data-flow programming model onto heterogeneous platforms. LCTES 2012: 61-70

Jason Cong, Glenn Reinman, Alex A. T. Bui, Vivek Sarkar: Customizable Domain-Specific Computing. IEEE Design & Test of Computers 28(2): 6-15 (2011)

Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong: Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Transactions 94-A(12): 2490-2498 (2011)

Jason Cong: Overview of Center for Domain-Specific Computing. J. Comput. Sci. Technol. 26(4): 632-635 (2011)

Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang: High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 473-491 (2011)

Jason Cong, Hui Huang, Wei Jiang: Pattern-Mining for Behavioral Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 30(6): 939-944 (2011)

Jason Cong, Wei Jiang, Bin Liu, Yi Zou: Automatic memory partitioning and scheduling for throughput and power optimization. ACM Trans. Design Autom. Electr. Syst. 16(2): 15 (2011)

Jeonghun Kim, Hanjun Choi, Sungyeal Yoon, Taesik Bang, Jongchan Park, Chaehyun Jung, Jason Cong: An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications. IEEE Trans. VLSI Syst. 19(8): 1490-1495 (2011)

Jason Cong: Era of customization and specialization. ASAP 2011: 3

Jason Cong, Beayna Grigorian, Glenn Reinman, Marco Vitanza: Accelerating vision and navigation applications on a customizable platform. ASAP 2011: 25-32

Jason Cong, Karthik Gururaj, Muhuan Huang, Sen Li, Bingjun Xiao, Yi Zou: Domain-specific processor with 3D integration for medical image processing. ASAP 2011: 247-250

Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong: Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC 2011: 261-266

Yu-Ting Chen, Jason Cong, Glenn Reinman: HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support. CODES+ISSS 2011: 295-304

Jason Cong, Guojie Luo, Yiyu Shi: Thermal-aware cell and through-silicon-via co-placement for 3D ICs. DAC 2011: 670-675

Jason Cong, Hui Huang, Chunyue Liu, Yi Zou: A reuse-aware prefetching scheme for scratchpad memory. DAC 2011: 960-965

Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong: Multilevel Granularity Parallelism Synthesis on FPGAs. FCCM 2011: 178-185

Jason Cong, Yi Zou: Resolving implicit barrier synchronizations in FPGA HLS (abstract only). FPGA 2011: 278

Jason Cong, Muhuan Huang, Yi Zou: Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms. FPL 2011: 50-57

Jason Cong, Karthik Gururaj: Assuring application-level correctness against soft errors. ICCAD 2011: 150-157

Jason Cong, Peng Zhang, Yi Zou: Combined loop transformation and hierarchy allocation for data reuse optimization. ICCAD 2011: 185-192

Jason Cong, Yuhui Huang, Bo Yuan: ATree-based topology synthesis for on-chip network. ICCAD 2011: 651-658

Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, M. Frank Chang: The DIMM tree architecture: A high bandwidth and scalable memory system. ICCD 2011: 388-395

Jason Cong, John Lee, Guojie Luo: A unified optimization framework for simultaneous gate sizing and placement under density constraints. ISCAS 2011: 1207-1210

Jason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman, Yi Zou: An energy-efficient adaptive hybrid cache. ISLPED 2011: 67-72

Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Hsieh-Hung Hsieh, P.-Y. Wu, Chewnpu Jou, Jason Cong, Glenn Reinman, Mau-Chung Frank Chang: An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling. ISSCC 2011: 488-490

Ming Yan, Jianwen Chen, Luminita A. Vese, John D. Villasenor, Alex A. T. Bui, Jason Cong: EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation. ISVC (1) 2011: 1-10

Jason Cong, Muhuan Huang, Yi Zou: 3D recursive Gaussian IIR on GPU and FPGAs - A case for accelerating bandwidth-bounded applications. SASP 2011: 70-73

Robert K. Brayton, Jason Cong: NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Design & Test of Computers 27(2): 68-74 (2010)

Robert K. Brayton, Jason Cong: NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Design & Test of Computers 27(3): 62-74 (2010)

Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng: Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1709-1722 (2010)

Jason Cong, Puneet Gupta, John Lee: Evaluating Statistical Power Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1750-1762 (2010)

Jason Cong, Bin Liu, Rupak Majumdar, Zhiru Zhang: Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. ACM Trans. Design Autom. Electr. Syst. 16(1): 4 (2010)

Deming Chen, Jason Cong, Yiping Fan, Lu Wan: LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. IEEE Trans. VLSI Syst. 18(4): 564-577 (2010)

Thorlindur Thorolfsson, Guojie Luo, Jason Cong, Paul D. Franzon: Logic-on-logic 3D integration and placement. 3DIC 2010: 1-4

Jason Cong, Chunyue Liu, Glenn Reinman: ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. DAC 2010: 443-448

Jason Cong, Kirill Minkovich: LUT-based FPGA technology mapping for reliability. DAC 2010: 517-522

Jason Cong, Hui Huang, Wei Jiang: A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis. DATE 2010: 1255-1260

Jason Cong, Bin Liu, Junjuan Xu: Coordinated resource optimization in behavioral synthesis. DATE 2010: 1267-1272

Jason Cong, Yi Zou: A Comparative Study on the Architecture Templates for Dynamic Nested Loops. FCCM 2010: 251-254

Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong: Bit-level optimization for high-level synthesis and FPGA-based acceleration. FPGA 2010: 59-68

Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan, Yi Zou: Accelerating Monte Carlo based SSTA using FPGA. FPGA 2010: 111-114

Jason Cong, Kirill Minkovich: LUT-based FPGA technology mapping for reliability (abstract only). FPGA 2010: 288

Jason Cong, Guojie Luo: An analytical placer for mixed-size 3D placement. ISPD 2010: 61-66

Jason Cong, Wolfgang Rosenstiel: The Last Byte: The HLS tipping point. IEEE Design & Test of Computers 26(4): 104 (2009)

Jason Cong, Yiping Fan, Junjuan Xu: Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. ACM Trans. Design Autom. Electr. Syst. 14(3) (2009)

Jason Cong, Yi Zou: FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation. TRETS 2(3) (2009)

Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang: Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. IEEE Trans. VLSI Syst. 17(9): 1318-1329 (2009)

Jason Cong, Puneet Gupta, John Lee: On the futility of statistical power optimization. ASP-DAC 2009: 167-172

Jason Cong, Guojie Luo: A multilevel analytical placement for 3D ICs. ASP-DAC 2009: 361-366

Jason Cong, Albert Liu, Bin Liu: A variation-tolerant scheduler for better than worst-case behavioral synthesis. CODES+ISSS 2009: 221-228

Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork: Moore's Law: another casualty of the financial meltdown? DAC 2009: 202-203

Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach: From milliwatts to megawatts: system level power challenge. DAC 2009: 750-751

Jason Cong, Karthik Gururaj: Energy efficient multiprocessor task scheduling under input-dependent variation. DATE 2009: 411-416

Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou: Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. FCCM 2009: 231-234

Jason Cong, Karthik Gururaj, Guoling Han: Synthesis of reconfigurable high-performance multicore systems. FPGA 2009: 201-208

Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou: Revisiting bitwidth optimizations. FPGA 2009: 278

Jason Cong: Customizable domain-specific computing. FPL 2009: 1

Jason Cong, Bin Liu, Zhiru Zhang: Scheduling with soft constraints. ICCAD 2009: 47-54

Tony F. Chan, Jason Cong, Eric Radke: A rigorous framework for convergent net weighting schemes in timing-driven placement. ICCAD 2009: 288-294

Jason Cong, Yi Zou: Parallel multi-level analytical global placement on graphics processing units. ICCAD 2009: 681-688

Jason Cong, Wei Jiang, Bin Liu, Yi Zou: Automatic memory partitioning and scheduling for throughput and power optimization. ICCAD 2009: 697-704

Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu: High-performance CUDA kernel execution on FPGAs. ICS 2009: 515-516

Jason Cong, Bin Liu, Zhiru Zhang: Behavior-level observability don't-cares and application to low-power behavioral synthesis. ISLPED 2009: 139-144

Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng, Mishali Naik, Lixia Zhang, Jason Cong: A scalable micro wireless interconnect structure for CMPs. MOBICOM 2009: 217-228

Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu: FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. SASP 2009: 35-42

Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam: Multiband RF-interconnect for reconfigurable network-on-chip communications. SLIP 2009: 107-108

Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong: Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. JETC 4(4) (2008)

Yuan Xie, Jason Cong, Paul D. Franzon: Editorial: Special issue on 3D integrated circuits and microarchitectures. JETC 4(4) (2008)

Jason Cong, Min Xie: A Robust Mixed-Size Legalization and Detailed Placement Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1349-1362 (2008)

Jason Cong, Guojie Luo, Eric Radke: Highly Efficient Gradient Computation for Density-Constrained Analytical Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2133-2144 (2008)

Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang: Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ASP-DAC 2008: 10-15

Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong: Scheduling with integer time budgeting for low-power optimization. ASP-DAC 2008: 22-27

Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong: LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212

Jason Cong, Junjuan Xu: Simultaneous FU and Register Binding Based on Network Flow Method. DATE 2008: 1057-1062

Kirill Minkovich, Jason Cong: Mapping for better than worst-case delays in LUT-based FPGA designs. FPGA 2008: 56-64

Jason Cong, Yi Zou: Lithographic aerial image simulation with FPGA-based hardwareacceleration. FPGA 2008: 67-76

Jason Cong, Wei Jiang: Pattern-based behavior synthesis for FPGA resource reduction. FPGA 2008: 107-116

M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam: CMP network-on-chip overlaid with multi-band RF-interconnect. HPCA 2008: 191-202

Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman: MC-Sim: an efficient simulation tool for MPSoC designs. ICCAD 2008: 364-371

Amit Agarwal, Jason Cong, Brian Tagiku: Fault tolerant placement and defect reconfiguration for nano-FPGAs. ICCAD 2008: 714-721

Jason Cong, John Lee, Lieven Vandenberghe: Robust gate sizing via mean excess delay minimization. ISPD 2008: 10-14

Jason Cong, Guojie Luo: Highly efficient gradient computation for density-constrained analytical placement methods. ISPD 2008: 39-46

M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman: RF interconnects for communications on-chip. ISPD 2008: 78-83

M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam: Power reduction of CMP communication networks via RF-interconnects. MICRO 2008: 376-387

Jason Cong: A new generation of C-base synthesis tool and domain-specific computing. SoCC 2008: 386

Jason Cong, Yuzheng Ding: FPGA Technology Mapping. Encyclopedia of Algorithms 2008

Jason Cong, Kirill Minkovich: Optimality Study of Logic Synthesis for LUT-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 230-239 (2007)

Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden: Routability-Driven Placement and White Space Allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 858-871 (2007)

Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski: Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Trans. Parallel Distrib. Syst. 18(8): 1094-1107 (2007)

Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang: High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC 2007: 529-534

Jason Cong, Guojie Luo, Jie Wei, Yan Zhang: Thermal-Aware 3D IC Placement Via Transformation. ASP-DAC 2007: 780-785

Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou: Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925

Jason Cong, Guoling Han, Wei Jiang: Synthesis of an application-specific soft multiprocessor system. FPGA 2007: 99-107

Jason Cong, Kirill Minkovich: Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. FPGA 2007: 139-147

Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong: Fine grain 3D integration for microarchitecture design through cube packing exploration. ICCD 2007: 259-266

Deming Chen, Jason Cong, Peichen Pan: FPGA Design Automation: A Survey. Foundations and Trends in Electronic Design Automation 1(3) (2006)

Jason Cong, Michail Romesis, Joseph R. Shinnerl: Fast floorplanning by look-ahead enabled recursive bipartitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1719-1732 (2006)

Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong: Protecting Combinational Logic Synthesis Solutions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2687-2696 (2006)

Deming Chen, Jason Cong, Junjuan Xu: Optimal simultaneous module and multivoltage assignment for low power. ACM Trans. Design Autom. Electr. Syst. 11(2): 362-386 (2006)

Gang Chen, Jason Cong: Simultaneous placement with clustering and duplication. ACM Trans. Design Autom. Electr. Syst. 11(3): 740-772 (2006)

Jason Cong, Guoling Han, Zhiru Zhang: Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. IEEE Trans. VLSI Syst. 14(9): 986-997 (2006)

Jason Cong, Min Xie: A robust detailed placement for mixed-size IC designs. ASP-DAC 2006: 188-194

Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang: An automated design flow for 3D microarchitecture evaluation. ASP-DAC 2006: 384-389

Jason Cong, Zhiru Zhang: An efficient and versatile scheduling algorithm based on SDC formulation. DAC 2006: 433-438

Joey Y. Lin, Deming Chen, Jason Cong: Optimal simultaneous mapping and clustering for FPGA delay optimization. DAC 2006: 472-477

Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu: Optimality study of resource binding with multi-Vdds. DAC 2006: 580-585

Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang: Behavior and communication co-optimization for systems with sequential communication media. DAC 2006: 675-678

Jason Cong, Kirill Minkovich: Optimality study of logic synthesis for LUT-based FPGAs. FPGA 2006: 33-40

Jason Cong, Yiping Fan, Wei Jiang: Platform-based resource binding using a distributed register-file microarchitecture. ICCAD 2006: 709-715

Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie: mPL6: enhanced multilevel mixed-size placement. ISPD 2006: 212-214

Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang: Platform-Based Behavior-Level and System-Level Synthesis. SoCC 2006: 199-202

Jason Cong, Jie Fang, Min Xie, Yan Zhang: MARS-a multilevel full-chip gridless routing system. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 382-394 (2005)

Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong: Power modeling and characteristics of field programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1712-1724 (2005)

Jason Cong, Hui Huang, Xin Yuan: Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 10(1): 3-23 (2005)

Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan: Large-scale circuit placement. ACM Trans. Design Autom. Electr. Syst. 10(2): 389-430 (2005)

Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong: Microarchitecture evaluation with floorplanning and interconnect pipelining. ASP-DAC 2005: 8-15

Jason Cong, Yan Zhang: Thermal-driven multilevel routing for 3-D ICs. ASP-DAC 2005: 121-126

Deming Chen, Jason Cong, Junjuan Xu: Optimal module and voltage assignment for low-power. ASP-DAC 2005: 850-855

Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng: Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC 2005: 856-861

Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe: Are we ready for system-level synthesis? ASP-DAC 2005

Jason Cong, Michail Romesis, Joseph R. Shinnerl: Fast floorplanning by look-ahead enabled recursive bipartitioning. ASP-DAC 2005: 1119-1122

Gang Chen, Jason Cong: Simultaneous timing-driven placement and duplication. FPGA 2005: 51-59

Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang: Instruction set extension with shadow registers for configurable processors. FPGA 2005: 99-106

Jason Cong, Michail Romesis, Joseph R. Shinnerl: Robust mixed-size placement under tight white-space constraints. ICCAD 2005: 165-172

Jason Cong, Guoling Han, Zhiru Zhang: Architecture and compilation for data bandwidth improvement in configurable embedded processors. ICCAD 2005: 263-270

Jason Cong, Yan Zhang: Thermal via planning for 3-D ICs. ICCAD 2005: 745-752

Junjuan Xu, Jason Cong, Xu Cheng: Lower-bound estimation for multi-bitwidth scheduling. ISCAS (1) 2005: 696-699

Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir: Understanding the energy efficiency of SMT and CMP with multiclustering. ISLPED 2005: 48-53

Tony F. Chan, Jason Cong, Kenton Sze: Multilevel generalized force-directed method for circuit placement. ISPD 2005: 185-192

Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie: mPL6: a robust multilevel mixed-size placement engine. ISPD 2005: 227-229

Jason Cong, Sung Kyu Lim: Edge separability-based circuit clustering with application to multilevel circuit partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 346-357 (2004)

Chin-Chih Chang, Jason Cong, Michail Romesis, Min Xie: Optimality and scalability study of existing placement algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 537-549 (2004)

Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang: Architecture and synthesis for on-chip multicycle communication. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 550-564 (2004)

Jason Cong, Sung Kyu Lim: Retiming-based timing analysis with an application to mincut-based global placement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1684-1692 (2004)

Deming Chen, Jason Cong: Register binding and port assignment for multiplexer optimization. ASP-DAC 2004: 68-73

Nitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar: What happened to ASIC?: Go (recon)figure? DAC 2004: 185

Jason Cong, Yiping Fan, Zhiru Zhang: Architecture-level synthesis for automatic interconnect pipelining. DAC 2004: 602-607

Fei Li, Yan Lin, Lei He, Jason Cong: Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA 2004: 42-50

Deming Chen, Jason Cong, Fei Li, Lei He: Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117

Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang: Application-specific instruction generation for configurable processor architectures. FPGA 2004: 183-189

Gang Chen, Jason Cong: Simultaneous Timing Driven Clustering and Placement for FPGAs. FPL 2004: 158-167

Jason Cong, Jie Wei, Yan Zhang: A thermal-driven floorplanning algorithm for 3D ICs. ICCAD 2004: 306-313

Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden: Routability-driven placement and white space allocation. ICCAD 2004: 394-401

Deming Chen, Jason Cong: DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. ICCAD 2004: 752-759

Deming Chen, Jason Cong: Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ISLPED 2004: 70-73

Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl: An area-optimality study of floorplanning. ISPD 2004: 78-83

Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan: Multilevel global placement with congestion control. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 395-409 (2003)

Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003)

Chin-Chih Chang, Jason Cong, Xin Yuan: Multi-level placement for large-scale mixed-size IC designs. ASP-DAC 2003: 325-330

Chin-Chih Chang, Jason Cong, Min Xie: Optimality and scalability study of existing placement algorithms. ASP-DAC 2003: 621-627

Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang: Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS 2003: 77-78

Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis: Microarchitecture evaluation with physical planning. DAC 2003: 32-35

Jason Cong, Xin Yuan: Multilevel global placement with retiming. DAC 2003: 208-213

Fei Li, Deming Chen, Lei He, Jason Cong: Architecture evaluation for power-efficient FPGAs. FPGA 2003: 175-184

Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze: An Enhanced Multilevel Algorithm for Circuit Placement. ICCAD 2003: 299-306

Jason Cong, Michail Romesis, Min Xie: Optimality and Stability Study of Timing-Driven Placement Algorithms. ICCAD 2003: 472-479

Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong: Gradual Relaxation Techniques with Applications to Behavioral Synthesis. ICCAD 2003: 529-535

Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang: Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. ICCAD 2003: 536-543

Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan: Large-Scale Circuit Placement: Gap and Promise. ICCAD 2003: 883-890

Deming Chen, Jason Cong, Yiping Fan: Low-power high-level synthesis for FPGA architectures. ISLPED 2003: 134-139

Jason Cong, Michail Romesis, Min Xie: Optimality, scalability and stability study of partitioning and placement algorithms. ISPD 2003: 88-94

Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang: Architecture and synthesis for multi-cycle communication. ISPD 2003: 190-196

Jason Cong, David Zhigang Pan: Wire width planning for interconnect performance optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 319-329 (2002)

Taku Uchino, Jason Cong: An interconnect energy model considering coupling effects. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 763-776 (2002)

Jason Cong, Yizhou Lin, Wangning Long: SPFD-based global rewiring. FPGA 2002: 77-84

Jason Cong, Min Xie, Yan Zhang: An enhanced multilevel routing system. ICCAD 2002: 51-58

Jason Cong, Joey Y. Lin, Wangning Long: A new enhanced SPFD rewiring algorithm. ICCAD 2002: 672-678

Chin-Chih Chang, Jason Cong, David Zhigang Pan: Physical hierarchy generation with routing congestion control. ISPD 2002: 36-41

Jason Cong, Chang Wu: Global clustering-based performance-driven circuit partitioning. ISPD 2002: 149-154

Jason Cong: Timing closure based on physical hierarchy. ISPD 2002: 170-174

Jason Cong, Joey Y. Lin, Wangning Long: Enhanced SPFD Rewiring on Improving Rewiring Ability. IWLS 2002: 91-96

Chin-Chih Chang, Jason Cong: Pseudopin assignment with crosstalk noise control. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 598-611 (2001)

Jason Cong, Jie Fang, Kei-Yong Khoo: DUNE-a multilayer gridless routing system. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 633-647 (2001)

Jason Cong, David Zhigang Pan: Interconnect performance estimation models for design planning. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 739-752 (2001)

Jason Cong, Yean-Yow Hwang: Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1077-1090 (2001)

Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001)

Jason Cong, Cheng-Kok Koh, Patrick H. Madden: Interconnect layout optimization under higher order RLC model forMCM designs. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1455-1463 (2001)

Jason Cong, Tianming Kong, Z. D. Pan: Buffer block planning for interconnect planning and prediction. IEEE Trans. VLSI Syst. 9(6): 929-937 (2001)

Jason Cong, David Zhigang Pan, Prasanna V. Srinivas: Improved crosstalk modeling for noise constrained interconnect optimization. ASP-DAC 2001: 373-378

Jason Cong, Michail Romesis: Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. DAC 2001: 389-394

Taku Uchino, Jason Cong: An Interconnect Energy Model Considering Coupling Effects. DAC 2001: 555-558

Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. FPGA 2001: 39-47

Gang Chen, Jason Cong: Simultaneous logic decomposition with technology mapping in FPGA designs. FPGA 2001: 48-55

Jason Cong, Jie Fang, Yan Zhang VI: Multilevel Approach to Full-Chip Gridless Routing. ICCAD 2001: 396-403

Jason Cong, Jie Fang, Kei-Yong Khoo: Via design rule consideration in multilayer maze routing algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 215-223 (2000)

Jason Cong, Songjie Xu: Performance-driven technology mapping for heterogeneous FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1268-1281 (2000)

Jason Cong, Yean-Yow Hwang: Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. ACM Trans. Design Autom. Electr. Syst. 5(2): 193-225 (2000)

Jason Cong, Songjie Xu: Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. ASP-DAC 2000: 157-162

Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu: Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. ASP-DAC 2000: 277-282

Jason Cong, Sung Kyu Lim: Edge separability based circuit clustering with application to circuit partitioning. ASP-DAC 2000: 429-434

Jason Cong, Sung Kyu Lim: Performance driven multiway partitioning. ASP-DAC 2000: 441-446

Maogang Wang, Sung Lim, Jason Cong, Majid Sarrafzadeh: Multi-way partitioning using bi-partition heuristics. ASP-DAC 2000: 667

Jason Cong, Sung Kyu Lim, Chang Wu: Performance driven multi-level and multiway partitioning with retiming. DAC 2000: 274-279

Jason Cong, Hui Huang: Depth optimal incremental mapping for field programmable gate arrays. DAC 2000: 290-293

Jason Cong, Xin Yuan: Routing tree construction under fixed buffer locations. DAC 2000: 379-384

Jason Cong, Hui Huang, Xin Yuan: Technology mapping for k/m-macrocell based FPGAs. FPGA 2000: 51-59

Jason Cong, Kenneth Yan: Synthesis for FPGAs with embedded memory blocks. FPGA 2000: 75-82

Jason Cong, Sung Kyu Lim: Physical Planning with Retiming. ICCAD 2000: 2-7

Tony F. Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl: Multilevel Optimization for Large-Scale Circuit Placement. ICCAD 2000: 171-176

Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh: Incremental CAD. ICCAD 2000: 236-243

Jason Cong, Jie Fang, Kei-Yong Khoo: DUNE: a multi-layer gridless routing system with wire planning. ISPD 2000: 12-18

Chin-Chih Chang, Jason Cong: Pseudo pin assignment with crosstalk noise control. ISPD 2000: 41-47

Jason Cong, Majid Sarrafzadeh: Incremental physical design. ISPD 2000: 84-92

Jason Cong, Lei He: Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 406-420 (1999)

Chin-Chih Chang, Jason Cong: An efficient approach to multilayer layer assignment with anapplication to via minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 608-620 (1999)

Jason Cong, Chang Wu: Optimal FPGA mapping and retiming with efficient initial state computation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1595-1607 (1999)

Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong: Relaxed Simulated Tempering for VLSI Floorplan Designs. ASP-DAC 1999: 13-16

Jason Cong, David Zhigang Pan: Interconnect Delay Estimation Models for Synthesis and Design Planning. ASP-DAC 1999: 97-100

Jason Cong, Yean-Yow Hwang, Songjie Xu: Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. DAC 1999: 373-378

Jason Cong, Honching Li, Chang Wu: Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. DAC 1999: 460-465

Jason Cong, David Zhigang Pan: Interconnect Estimation and Dlanning for Deep Submicron Designs. DAC 1999: 507-510

Jason Cong, Chang Wu, Yuzheng Ding: Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. FPGA 1999: 29-35

Jason Cong, Jie Fang, Kei-Yong Khoo: An implicit connection graph maze routing algorithm for ECO routing. ICCAD 1999: 163-167

Jason Cong, Tianming Kong, David Zhigang Pan: Buffer block planning for interconnect-driven floorplanning. ICCAD 1999: 358-363

Jason Cong, Jie Fang, Kei-Yong Khoo: VIA design rule consideration in multi-layer maze routing algorithms. ISPD 1999: 214-220

Farid N. Najm, Jason Cong, David Blaauw (Eds.): Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999. ACM 1999, isbn 1-58113-133-X

Jason Cong, Andrew B. Kahng, Kwok-Shing Leung: Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 24-39 (1998)

Jason Cong, Chang Wu: An efficient algorithm for performance-optimal FPGA technology mapping with retiming. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 738-748 (1998)

Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998)

Jason Cong, Chang Wu: Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. DAC 1998: 330-335

Jason Cong, Patrick H. Madden: Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. DAC 1998: 356-361

Jason Cong, Songjie Xu: Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. DAC 1998: 704-707

Jason Cong, Yean-Yow Hwang: Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. FPGA 1998: 27-34

Jason Cong, Songjie Xu: Technology Mapping for FPGAs with Embedded Memory Blocks. FPGA 1998: 179-188

Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne Wolf: How will CAD handle billion-transistor systems? (panel). ICCAD 1998: 5

Jason Cong, Songjie Xu: Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources. ICCAD 1998: 40-44

Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong: Intellectual property protection by watermarking combinational logic synthesis solutions. ICCAD 1998: 194-198

Jason Cong, Sung Kyu Lim: Multiway partitioning with pairwise movement. ICCAD 1998: 512-516

Jason Cong, Lei He: An efficient technique for device and interconnect optimization in deep submicron designs. ISPD 1998: 45-51

Jason Cong, Patrick H. Madden: Performance-driven routing with multiple sources. IEEE Trans. on CAD of Integrated Circuits and Systems 16(4): 410-419 (1997)

Chin-Chih Chang, Jason Cong: An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. DAC 1997: 600-603

Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen: Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC 1997: 627-632

Jason Cong, Chang Wu: FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. DAC 1997: 644-649

Jason Cong, John Peck: On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. FCCM 1997: 246-248

Jason Cong, Yean-Yow Hwang: Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. FPGA 1997: 35-42

Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu: Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. ICCAD 1997: 441-446

Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo: Interconnect design for deep submicron ICs. ICCAD 1997: 478-485

Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633

Jason Cong, Cheng-Kok Koh: Interconnect layout optimization under higher-order RLC model. ICCAD 1997: 713-720

Jason Cong, Patrick H. Madden: Performance driven global routing for standard cell design. ISPD 1997: 73-80

Jason Cong, Andrew B. Kahng, Kwok-Shing Leung: Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. ISPD 1997: 88-95

Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden: Performance optimization of VLSI interconnect layout. Integration 21(1-2): 1-94 (1996)

Jason Cong, Wilburt Labio, Narayanan Shivakumar: Multiway VLSI circuit partitioning based on dual net representation. IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 396-409 (1996)

Jason Cong, Yuzheng Ding: Combinational logic synthesis for LUT based field programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. 1(2): 145-204 (1996)

Jason Cong, Lei He: Optimal wiresizing for interconnects with multiple sources. ACM Trans. Design Autom. Electr. Syst. 1(4): 478-511 (1996)

Jason Cong, Yean-Yow Hwang: Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. DAC 1996: 726-729

Jason Cong, John Peck, Yuzheng Ding: RASP: A General Logic Synthesis System for SRAM-Based FPGAs. FPGA 1996: 137-143

Takumi Okamoto, Jason Cong: Buffered Steiner tree construction with wire sizing for interconnect layout optimization. ICCAD 1996: 44-49

Jason Cong, Lei He: An efficient approach to simultaneous transistor and interconnect sizing. ICCAD 1996: 181-186

Jason Cong, Chang Wu: An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. ICCD 1996: 572-578

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung: Simultaneous buffer and wire sizing for performance and power optimization. ISLPED 1996: 271-276

Leonard Kleinrock, Mario Gerla, Nicholas Bambos, Jason Cong, Eli Gafni, Larry Bergman, Joseph A. Bannister: The Supercomputer Supernet: A Scalable Distributed Terabit Network. J. High Speed Networks 4(4): 407-424 (1995)

Jason Cong, Kwok-Shing Leung: Optimal wiresizing under Elmore delay model. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 321-336 (1995)

Kei-Yong Khoo, Jason Cong: An efficient multilayer MCM router based on four-via routing. IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1277-1290 (1995)

Jason Cong, Dongmin Xu: Exploitation signal flow and logic dependency in standard cell placement. ASP-DAC 1995

Jason Cong, Yean-Yow Hwang: Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. FPGA 1995: 68-74

Jason Cong, Yuzheng Ding: On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. FPGA 1995: 82-88

Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao: Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71

Jason Cong, Lei He: Optimal wiresizing for interconnects with multiple sources. ICCAD 1995: 568-574

Jason Cong, Patrick H. Madden: Performance Driven Routing with Mulitiple Sources. ISCAS 1995: 203-206

Jason Cong, Cheng-Kok Koh: Minimum-Cost Bounded-Skew Clock Routing. ISCAS 1995: 215-218

Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen: LUT-based FPGA technology mapping under arbitrary net-delay models. Computers & Graphics 18(4): 507-516 (1994)

Jason Cong, Yuzheng Ding: On nominal delay minimization in LUT-based FPGA technology mapping. Integration 18(1): 73-94 (1994)

Jason Cong, Yuzheng Ding: FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 1-12 (1994)

Jason Cong, Yuzheng Ding: On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans. VLSI Syst. 2(2): 137-148 (1994)

Jason Cong, Cheng-Kok Koh: Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. VLSI Syst. 2(4): 408-425 (1994)

Jason Cong, Zheng Li, Rajive Bagrodia: Acyclic Multi-Way Partitioning of Boolean Networks. DAC 1994: 670-675

Jason Cong, Wilburt Labio, Narayanan Shivakumar: Multi-way VLSI circuit partitioning based on dual net representation. ICCAD 1994: 56-62

Jason Cong, Cheng-Kok Koh: Simultaneous driver and wire sizing for performance and power optimization. ICCAD 1994: 206-212

Rajive Bagrodia, Zheng Li, Vikas Jha, Yuan Chen, Jason Cong: Parallel logic level simulation of VLSI circuits. Winter Simulation Conference 1994: 1354-1361

Jason Cong, Moazzem Hossain, Naveed A. Sherwani: A provably good multilayer topological planar routing algorithm in IC layout designs. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 70-78 (1993)

Jason Cong, Bryan Preas, C. L. Liu: Physical models and efficient algorithms for over-the-cell routing in standard cell design. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 723-734 (1993)

Jason Cong, Andrew B. Kahng, Gabriel Robins: Matching-based methods for high-performance clock routing. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1157-1169 (1993)

Jason Cong, Yuzheng Ding: On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. DAC 1993: 213-218

Kei-Yong Khoo, Jason Cong: An Efficient Multilayer MCM Router Based on Four-Via Routing. DAC 1993: 590-595

Jason Cong, Kwok-Shing Leung, Dian Zhou: Performance-Driven Interconnect Design Based on Distributed RC Delay Model. DAC 1993: 606-611

Jason Cong, M'Lissa Smith: A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. DAC 1993: 755-760

Jason Cong, Yuzheng Ding: Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. ICCAD 1993: 110-114

Jason Cong, Kwok-Shing Leung: Optimal wiresizing under the distributed Elmore delay model. ICCAD 1993: 634-639

Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh: Minimum Density Interconneciton Trees. ISCAS 1993: 1865-1868

Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong: A Two-pole Circuit Model for VLSI High-speed Interconnection. ISCAS 1993: 2129-2132

Jason Cong, Moazzem Hossain, Naveed A. Sherwani: A Provably Good Algorithm for k-Layer Topological Planar Routing Problems. VLSI Design 1993: 113

Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar: DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Design & Test of Computers 9(3): 7-20 (1992)

Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong: Provably good performance-driven global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 739-752 (1992)

Jason Cong, Lars W. Hagen, Andrew B. Kahng: Net Partitions Yield Better Module Partitions. DAC 1992: 47-52

Jason Cong, Yuzheng Ding: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. ICCAD 1992: 48-53

Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen: An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD 1992: 154-158

Khe-Sing The, Martin D. F. Wong, Jason Cong: A layout modification approach to via minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 536-541 (1991)

Jason Cong, C. L. Liu: On the k-layer planar subset and topological via minimization problems. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 972-981 (1991)

Jason Cong: Pin assignment with global routing for general cell designs. IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1401-1412 (1991)

Andrew B. Kahng, Jason Cong, Gabriel Robins: High-Performance Clock Routing Based on Recursive Geometric Aatching. DAC 1991: 322-327

Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong: Performance-Driven Global Routing for Cell Based ICs. ICCD 1991: 170-173

Jason Cong, Kei-Yong Khoo: A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. ICCD 1991: 319-322

Jason Cong, C. L. Liu: Over-the-cell channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 408-418 (1990)

Jason Cong, Bryan Preas, C. L. Liu: General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. DAC 1990: 709-715

Jason Cong, C. L. Liu: On the k-layer planar subset and via minimization problems. EURO-DAC 1990: 459-463

Khe-Sing The, D. F. Wong, Jason Cong: VIA Minimization by Layout Modification. DAC 1989: 799-802

Jason Cong, Martin D. F. Wong, C. L. Liu: A new approach to three- or four-layer channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1094-1104 (1988)