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Elio Consoli
2010 – today
- 2012
[j6]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo: An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits. IEEE Trans. on Circuits and Systems 59-I(1): 159-169 (2012)- [j5]Elio Consoli, Gaetano Palumbo, Melita Pennisi: Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops. IEEE Trans. VLSI Syst. 20(2): 284-295 (2012)
- [c11]Massimo Alioto, Elio Consoli, Jan M. Rabaey: EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS. CICC 2012: 1-4
- [c10]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo: Logic gates dynamic modeling by means of an ultra-compact MOS model. ISCAS 2012: 3250-3253
- [c9]Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey: Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. ISSCC 2012: 482-484
- 2011
- [j4]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies. IEEE Trans. VLSI Syst. 19(5): 725-736 (2011)
- [j3]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit. IEEE Trans. VLSI Syst. 19(5): 737-750 (2011)
- [c8]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo: Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model. ECCTD 2011: 512-515
- [c7]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo: An ultra-compact MOS model in nanometer technologies. ECCTD 2011: 520-523
- [c6]Elio Consoli, Gaetano Palumbo, Melita Pennisi: TG Master-Slave FFs: High-speed optimization. ISCAS 2011: 554-557
- [c5]Massimo Alioto, Elio Consoli, Gaetano Palumbo: DET FF topologies: A detailed investigation in the energy-delay-area domain. ISCAS 2011: 563-566
- 2010
- [j2]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design. IEEE Trans. on Circuits and Systems 57-I(6): 1273-1286 (2010)
- [j1]Massimo Alioto, Elio Consoli, Gaetano Palumbo: General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space. IEEE Trans. on Circuits and Systems 57-I(7): 1583-1596 (2010)
- [c4]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. ISCAS 2010: 321-324
- [c3]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits. PATMOS 2010: 62-72
2000 – 2009
- 2009
- [c2]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Optimum clock slope for flip-flops within a clock domain: Analysis and a case study. ICECS 2009: 275-278
- [c1]Massimo Alioto, Elio Consoli, Gaetano Palumbo: Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits. ISCAS 2009: 3150-3153
Coauthor Index
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last updated on 2012-12-02 21:20 CET by the dblp team