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George A. Constantinides
2010 – today
- 2013
[j40]Ammar Hasan, Eric C. Kerrigan, George A. Constantinides: Control-Theoretic Forward Error Analysis of Iterative Numerical Algorithms. IEEE Trans. Automat. Contr. 58(6): 1524-1529 (2013)- [j39]David Boland, George A. Constantinides: A Scalable Precision Analysis Framework. IEEE Transactions on Multimedia 15(2): 242-256 (2013)
- [c96]David Boland, George A. Constantinides: Word-length optimization beyond straight line code. FPGA 2013: 105-114
- [i1]Juan Luis Jerez, Paul J. Goulart, Stefan Richter, George A. Constantinides, Eric C. Kerrigan, Manfred Morari: Embedded Online Optimization for Model Predictive Control at Megahertz Rates. CoRR abs/1303.1090 (2013)
- 2012
- [j38]Juan Luis Jerez, Eric C. Kerrigan, George A. Constantinides: A sparse and condensed QP formulation for predictive control of LTI systems. Automatica 48(5): 999-1002 (2012)
- [j37]Samuel Bayliss, George A. Constantinides: Analytical synthesis of bandwidth-efficient SDRAM address generators. Microprocessors and Microsystems - Embedded Hardware Design 36(8): 665-675 (2012)
- [j36]Amir Shahzad, Eric C. Kerrigan, George A. Constantinides: A Stable and Efficient Method for Solving a Convex Quadratic Program with Application to Optimal Control. SIAM Journal on Optimization 22(4): 1369-1393 (2012)
- [j35]Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides: Optimizing Hardware Design by Composing Utility-Directed Transformations. IEEE Trans. Computers 61(12): 1800-1812 (2012)
- [j34]Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides: Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms. Signal Processing Systems 67(1): 65-78 (2012)
- [c95]Abid Rafique, Nachiket Kapre, George A. Constantinides: A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem. ARC 2012: 239-250
- [c94]Xuan You Tan, David Boland, George A. Constantinides: FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores. ARC 2012: 290-301
- [c93]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan: Towards a fixed point QP solver for predictive control. CDC 2012: 675-680
- [c92]José Gabriel F. Coutinho, Sujit Bhattacharya, Wayne Luk, George A. Constantinides, João M. P. Cardoso, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov: Resource-Efficient Designs Using an Aspect-Oriented Approach. CSE 2012: 399-406
- [c91]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan: Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing. FCCM 2012: 53-60
- [c90]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung: Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM 2012: 109-116
- [c89]David Boland, George A. Constantinides: A scalable approach for automated precision analysis. FPGA 2012: 185-194
- [c88]Samuel Bayliss, George A. Constantinides: Optimizing SDRAM bandwidth for custom FPGA loop accelerators. FPGA 2012: 195-204
- [c87]Abid Rafique, Nachiket Kapre, George A. Constantinides: Enhancing performance of Tall-Skinny QR factorization using FPGAs. FPL 2012: 443-450
- [c86]Zhenyu Guan, Justin S. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung: A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL 2012: 519-522
- [c85]Theo Drane, Wai-chuen Cheung, George A. Constantinides: Correctly rounded constant integer division via multiply-add. ISCAS 2012: 1243-1246
- 2011
- [j33]Stefano Longo, Eric C. Kerrigan, Keck Voon Ling, George A. Constantinides: A parallel formulation for predictive control with nonuniform hold constraints. Annual Reviews in Control 35(2): 207-214 (2011)
- [j32]Amir Shahzad, Bryn Ll. Jones, Eric C. Kerrigan, George A. Constantinides: An efficient algorithm for the solution of a coupled Sylvester equation appearing in descriptor systems. Automatica 47(1): 244-248 (2011)
- [j31]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. Comput. J. 54(1): 1-10 (2011)
- [j30]George A. Constantinides, Nicola Nicolici: Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research. IEEE Design & Test of Computers 28(4): 6-7 (2011)
- [j29]George A. Constantinides, Adam B. Kinsman, Nicola Nicolici: Numerical Data Representations for FPGA-Based Scientific Computing. IEEE Design & Test of Computers 28(4): 8-17 (2011)
- [j28]David Boland, George A. Constantinides: Bounding Variable Values and Round-Off Effects Using Handelman Representations. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1691-1704 (2011)
- [j27]David Boland, George A. Constantinides: Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods. TRETS 4(3): 22 (2011)
- [c84]Samuel Bayliss, George A. Constantinides: Application Specific Memory Access, Reuse and Reordering for SDRAM. ARC 2011: 41-52
- [c83]Manouk V. Manoukian, George A. Constantinides: Accurate Floating Point Arithmetic through Hardware Error-Free Transformations. ARC 2011: 94-101
- [c82]Christophe Le Lann, David Boland, George A. Constantinides: The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA. ARC 2011: 287-295
- [c81]Stefano Longo, Eric C. Kerrigan, Keck Voon Ling, George A. Constantinides: Parallel move blocking Model Predictive Control. CDC-ECE 2011: 1239-1244
- [c80]Ammar Hasan, Eric C. Kerrigan, George A. Constantinides: Solving a positive definite system of linear equations via the matrix exponential. CDC-ECE 2011: 2299-2304
- [c79]Juan Luis Jerez, Eric C. Kerrigan, George A. Constantinides: A condensed and sparse QP formulation for predictive control. CDC-ECE 2011: 5217-5222
- [c78]Theo Drane, George A. Constantinides: Optimisation of mutually exclusive arithmetic sum-of-products. DATE 2011: 1388-1393
- [c77]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan: An FPGA implementation of a sparse quadratic programming solver for constrained predictive control. FPGA 2011: 209-218
- [c76]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung: Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA 2011: 284
- 2010
- [j26]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: FPGA Architecture Optimization Using Geometric Programming. IEEE Trans. on CAD of Integrated Circuits and Systems 29(8): 1163-1176 (2010)
- [j25]Antonio Roldao Lopes, George A. Constantinides: A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices. TRETS 3(1) (2010)
- [j24]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. TRETS 3(3): 13 (2010)
- [j23]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides: An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator. TRETS 4(1): 2 (2010)
- [j22]Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. TRETS 4(1): 3 (2010)
- [c75]Antonio Roldao Lopes, George A. Constantinides: A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs. ARC 2010: 157-168
- [c74]David Boland, George A. Constantinides: Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods. ARC 2010: 169-181
- [c73]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides: Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA. ARC 2010: 182-193
- [c72]Amir Shahzad, Eric C. Kerrigan, George A. Constantinides: A fast well-conditioned interior point method for predictive control. CDC 2010: 508-513
- [c71]Ammar Hasan, Eric C. Kerrigan, George A. Constantinides: An ISS and l-stability approach to forward error analysis of iterative numerical algorithms. CDC 2010: 780-785
- [c70]Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides: Customizable Composition and Parameterization of Hardware Design Transformations. DSD 2010: 595-602
- [c69]David Boland, George A. Constantinides: Automated Precision Analysis: A Polynomial Algebraic Approach. FCCM 2010: 157-164
- [c68]Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides: A Scripting Engine for Combining Design Transformations. FCCM 2010: 255-258
- [c67]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides: Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA. FPL 2010: 89-94
- [c66]Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan: FPGA implementation of an interior point solver for linear model predictive control. FPT 2010: 316-319
2000 – 2009
- 2009
- [j21]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. IET Computers & Digital Techniques 3(3): 235-246 (2009)
- [j20]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 305-315 (2009)
- [j19]Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung: Word-length selection for power minimization via nonlinear optimization. ACM Trans. Design Autom. Electr. Syst. 14(3) (2009)
- [j18]Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung: Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. TRETS 1(4) (2009)
- [j17]Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. TRETS 2(4) (2009)
- [j16]Vanderlei Bonato, Eduardo Marques, George A. Constantinides: A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots. Signal Processing Systems 56(1): 41-50 (2009)
- [c65]Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung: Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ARC 2009: 133-144
- [c64]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides: Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator. ARC 2009: 231-242
- [c63]Antonio Roldao Lopes, Amir Shahzad, George A. Constantinides, Eric C. Kerrigan: More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control. FCCM 2009: 209-216
- [c62]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Area estimation and optimisation of FPGA routing fabrics. FPL 2009: 256-261
- [c61]Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides: Optimising designs by combining model-based and pattern-based transformations. FPL 2009: 308-313
- [c60]Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung: Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT 2009: 54-61
- 2008
- [j15]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: Custom parallel caching schemes for hardware-accelerated image compression. J. Real-Time Image Processing 3(4): 289-302 (2008)
- [j14]Vanderlei Bonato, Eduardo Marques, George A. Constantinides: A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection. IEEE Trans. Circuits Syst. Video Techn. 18(12): 1703-1712 (2008)
- [j13]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. IEEE Trans. VLSI Syst. 16(6): 733-744 (2008)
- [j12]George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong: Guest Editorial: Field Programmable Technology. Signal Processing Systems 51(1): 1-2 (2008)
- [c59]Antonio Roldao Lopes, George A. Constantinides: A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation. ARC 2008: 75-86
- [c58]Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC 2008: 124-135
- [c57]Vanderlei Bonato, Eduardo Marques, George A. Constantinides: A Parallel Hardware Architecture for Image Feature Detection. ARC 2008: 136-147
- [c56]Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides: Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA. ARC 2008: 231-242
- [c55]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. BCS Int. Acad. Conf. 2008: 295-304
- [c54]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL 2008: 179-184
- [c53]David Boland, George A. Constantinides: An FPGA-based implementation of the MINRES algorithm. FPL 2008: 379-384
- [c52]Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos: Co-optimisation of datapath and memory in outer loop pipelining. FPT 2008: 1-8
- [c51]Antonio Roldao Lopes, George A. Constantinides, Eric C. Kerrigan: A floating-point solver for band structured linear equations. FPT 2008: 353-356
- [c50]Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith: Glitch-aware output switching activity from word-level statistics. ISCAS 2008: 1792-1795
- 2007
- [j11]Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: ROM to DSP block transfer for resource constrained synthesis. IET Computers & Digital Techniques 1(1): 17-26 (2007)
- [j10]George A. Constantinides: Special issue on Field-Programmable Technology. J. Real-Time Image Processing 2(4): 177-178 (2007)
- [j9]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. VLSI Syst. 15(9): 1003-1016 (2007)
- [c49]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung: Automatic On-chip Memory Minimization for Data Reuse. FCCM 2007: 251-260
- [c48]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: A Hybrid Memory Sub-system for Video Coding Applications. FCCM 2007: 317-318
- [c47]Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung: On the feasibility of early routing capacitance estimation for FPGAs. FPL 2007: 234-239
- [c46]Vanderlei Bonato, Eduardo Marques, George A. Constantinides: A floating-point Extended Kalman Filter implementation for autonomous mobile robots. FPL 2007: 576-579
- [c45]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction. FPT 2007: 105-112
- 2006
- [j8]Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides: Accuracy-Guaranteed Bit-Width Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1990-2000 (2006)
- [j7]George A. Constantinides: Word-length optimization for differentiable nonlinear systems. ACM Trans. Design Autom. Electr. Syst. 11(1): 26-43 (2006)
- [c44]Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC 2006: 205-216
- [c43]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. FCCM 2006: 275-276
- [c42]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield enhancements of design-specific FPGAs. FPGA 2006: 93-100
- [c41]Su-Shin Ang, George A. Constantinides: Dynamic Memory Sub-System for Reconfigurable Platforms. FPL 2006: 1-2
- [c40]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL 2006: 1-6
- [c39]Jonathan A. Clarke, George A. Constantinides: High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic. FPL 2006: 1-2
- [c38]Konstantinos Masselos, George A. Constantinides, Qiang Liu: Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. FPL 2006: 1-6
- [c37]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. FPL 2006: 1-6
- [c36]Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong: FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. FPL 2006: 1-6
- [c35]Samuel Bayliss, Christos-Savvas Bouganis, George A. Constantinides, Wayne Luk: An FPGA implementation of the simplex algorithm. FPT 2006: 49-56
- [c34]Altaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides: PowerBit - power aware arithmetic bit-width optimization. FPT 2006: 289-292
- [c33]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: The cost of data dependence in motion vector estimation for reconfigurable platforms. FPT 2006: 333-336
- [c32]Altaf Abdul Gaffar, Jonathan A. Clarke, George A. Constantinides: Modeling of glitch effects in FPGA based arithmetic circuits. FPT 2006: 349-352
- [c31]Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung: Fast word-level power models for synthesis of FPGA-based arithmetic. ISCAS 2006
- [c30]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176
- [e2]George A. Constantinides, Wai-Kei Mak, Phaophak Sirisuk, Theerayod Wiangtong (Eds.): 2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006. IEEE 2006, ISBN 0-7803-9728-2
- 2005
- [j6]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. VLSI Syst. 13(1): 39-57 (2005)
- [c29]Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung: A Novel 2D Filter Design Methodology for Heterogeneous Devices. FCCM 2005: 13-22
- [c28]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. FPGA 2005: 138-148
- [c27]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: Exploration of heterogeneous reconfigurable architectures (abstract only). FPGA 2005: 268
- [c26]Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. FPL 2005: 77-82
- [c25]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Power and Area Optimization for Multiple Restricted Multiplication. FPL 2005: 112-117
- [c24]Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. FPL 2005: 124-129
- [c23]Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides: Heterogeneity Exploration for Multiple 2D Filter Designs. FPL 2005: 263-268
- [c22]Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides: FPGA-Accelerated Reconstruction of Gene Regulatory Networks. FPL 2005: 323-328
- [c21]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung: An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. FPL 2005: 341-346
- [c20]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. FPL 2005: 409-414
- [c19]Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides: Parameterized Logic Power Consumption Models for FPGA based Systems. FPL 2005: 626-629
- [c18]Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung: A novel 2D filter design methodology. ISCAS (1) 2005: 532-535
- [c17]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: A heuristic approach for multiple restricted multiplication. ISCAS (1) 2005: 692-695
- 2004
- [b1]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthesis and optimization of DSP algorithms. Kluwer 2004, ISBN 978-1-4020-7930-6, pp. I-XI, 1-164
- [j5]Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa: Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers 53(11): 1361-1362 (2004)
- [c16]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272
- [c15]George A. Constantinides, Abunaser Miah, Nalin Sidahao: Word-Length Optimization of Folded Polynomial Evaluation. FCCM 2004: 285-286
- [c14]Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung: Migrating Functionality from ROMS to Embedded Multipliers. FCCM 2004: 287-288
- [c13]Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides: Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. FPL 2004: 200-208
- [c12]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Multiple Restricted Multiplication. FPL 2004: 374-383
- [c11]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051
- 2003
- [j4]George A. Constantinides: Review of Computer arithmetic algorithms by Israel Koren. A.K. Peters. SIGACT News 34(3): 13-15 (2003)
- [j3]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Wordlength optimization for linear digital signal processing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1432-1442 (2003)
- [j2]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. 8(3): 334-354 (2003)
- [c10]
- [c9]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615
- [c8]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung: Architectures for function evaluation on FPGAs. ISCAS (2) 2003: 804-807
- [e1]Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa (Eds.): Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings. Lecture Notes in Computer Science 2778, Springer 2003, ISBN 3-540-40822-3
- 2002
- [j1]George A. Constantinides, Gerhard J. Woeginger: The complexity of multiple wordlength assignment. Appl. Math. Lett. 15(2): 137-140 (2002)
- [c7]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Optimum Wordlength Allocation. FCCM 2002: 219-228
- [c6]Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen: Strassen's matrix multiplication for customisable processors. FPT 2002: 453-456
- 2001
- [c5]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Heuristic datapath allocation for multiple wordlength systems. DATE 2001: 791-797
- [c4]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: The Multiple Wordlength Paradigm. FCCM 2001: 51-60
- 2000
- [c3]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple Precision for Resource Minimization. FCCM 2000: 307-308
- [c2]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Multiple-Wordlength Resource Binding. FPL 2000: 646-655
1990 – 1999
- 1999
- [c1]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. FPL 1999: 323-332
Coauthor Index
[c90] [c86] [j31] [c76] [j26] [j24] [j22] [j21] [j20] [j19] [j18] [j17] [c65] [c62] [c60] [j15] [j13] [c58] [c55] [c54] [c52] [c50] [j11] [j9] [c49] [c48] [c47] [c45] [c44] [c43] [c42] [c40] [c37] [c33] [c31] [c30] [j6] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c21] [c20] [c18] [c17] [b1] [j5] [c16] [c14] [c13] [c12] [c11] [j3] [j2] [c9] [c8] [e1] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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last updated on 2013-05-28 21:37 CEST by the dblp team