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 | 2012 | |
|---|---|---|
| c7 |      | Waleed Alkohlani, Jeanine Cook: Towards Performance Predictive Application-Dependent Workload Characterization. SC Companion 2012: 426-436 |
| 2011 | ||
| j3 | | Jeanine Cook, Jonathan Cook, Waleed Alkohlani: A statistical performance model of the opteron processor. SIGMETRICS Performance Evaluation Review 38(4): 75-80 (2011) |
| 2010 | ||
| c6 | | Waleed Alkohlani, Jeanine Cook, Ram Srinivasan: Extending the Monte Carlo Processor Modeling Technique: Statistical Performance Models of the Niagara 2 Processor. ICPP 2010: 363-374 |
| 2007 | ||
| j2 | | Ram Srinivasan, Eitan Frachtenberg, Olaf M. Lubeck, Scott Pakin, Jeanine Cook: An Idealistic Neuro-PPM Branch Predictor. J. Instruction-Level Parallelism 9 (2007) |
| c5 | | Santosh Talli, Ram Srinivasan, Jeanine Cook: Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization. IPCCC 2007: 372-379 |
| 2006 | ||
| j1 | | Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck: Performance modeling using Monte Carlo simulation. Computer Architecture Letters 5(1): 38-41 (2006) |
| c4 | | Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck: Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach. SBAC-PAD 2006: 107-116 |
| 2005 | ||
| c3 | | Ram Srinivasan, Jeanine Cook, Shaun Cooper: Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection. ISPASS 2005: 147-156 |
| c2 | | Wiplove Mathur, Jeanine Cook: Improved Estimation for Software Multiplexing of Performance Counters. MASCOTS 2005: 23-34 |
| 2002 | ||
| c1 | | Jeanine Cook, Richard L. Oliver, Eric E. Johnson: Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity. SIGMETRICS 2002: 252-253 |
| 1 | Waleed Alkohlani | |
| 2 | Jonathan Cook | |
| 3 | Shaun Cooper | |
| 4 | Eitan Frachtenberg | |
| 5 | Eric E. Johnson | |
| 6 | Olaf M. Lubeck | |
| 7 | Wiplove Mathur | |
| 8 | Richard L. Oliver | |
| 9 | Scott Pakin | |
| 10 | Ram Srinivasan | |
| 11 | Santosh Talli |
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