DBLP: Gwenolé Corre

	2008
j1		Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: Estimation et optimisation de la consommation des mémoires. Technique et Science Informatiques 27(1-2): 235-254 (2008)
	2006
i5		Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin: Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power. CoRR abs/cs/0605142 (2006)
i4		Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin: High-level synthesis under I/O Timing and Memory constraints. CoRR abs/cs/0605143 (2006)
i3		Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin: A Memory Aware High Level Synthesis Too. CoRR abs/cs/0605144 (2006)
i2		Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: Memory Aware High-Level Synthesis for Embedded Systems. CoRR abs/cs/0605145 (2006)
i1		Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin: Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI. CoRR abs/cs/0605146 (2006)
	2005
c5		Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin: High-level synthesis under I/O timing and memory constraints. ISCAS (1) 2005: 680-683
	2004
c4		Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin: Memory accesses management during high level synthesis. CODES+ISSS 2004: 42-47
c3		Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: Memory Aware HLS and the Implementation of Ageing Vectors. DSD 2004: 88-95
c2		Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: A memory aware behavioral synthesis tool for real-time VLSI circuits. ACM Great Lakes Symposium on VLSI 2004: 82-85
c1		Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: A Memory Aware High Level Synthesis Tool . ISVLSI 2004: 279-280

2008

Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: Estimation et optimisation de la consommation des mémoires. Technique et Science Informatiques 27(1-2): 235-254 (2008)

2006

Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin: Intégration de la synthèse mémoire dans l'outil de synthèse d'architecture GAUT Low Power. CoRR abs/cs/0605142 (2006)

Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin: High-level synthesis under I/O Timing and Memory constraints. CoRR abs/cs/0605143 (2006)

Gwenolé Corre, Nathalie Julien, Eric Senn, Eric Martin: A Memory Aware High Level Synthesis Too. CoRR abs/cs/0605144 (2006)

Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: Memory Aware High-Level Synthesis for Embedded Systems. CoRR abs/cs/0605145 (2006)

Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin: Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI. CoRR abs/cs/0605146 (2006)

2005

Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin: High-level synthesis under I/O timing and memory constraints. ISCAS (1) 2005: 680-683

2004

Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin: Memory accesses management during high level synthesis. CODES+ISSS 2004: 42-47

Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: Memory Aware HLS and the Implementation of Ageing Vectors. DSD 2004: 88-95

Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: A memory aware behavioral synthesis tool for real-time VLSI circuits. ACM Great Lakes Symposium on VLSI 2004: 82-85

Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin: A Memory Aware High Level Synthesis Tool . ISVLSI 2004: 279-280

1	Pierre Bomel	[i4] [i1] [c5] [c4]
2	Philippe Coussy	[i4] [i1] [c5]
3	Nathalie Julien	[j1] [i5] [i3] [i2] [c4] [c3] [c2] [c1]
4	Eric Martin 0001	[j1] [i5] [i4] [i3] [i2] [i1] [c5] [c4] [c3] [c2] [c1]
5	Eric Senn	[j1] [i5] [i4] [i3] [i2] [i1] [c5] [c4] [c3] [c2] [c1]

Gwenolé Corre

Coauthor Index