Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Philippe Coussy
2010 – today
- 2013
[j9]V. Lapôtre, Philippe Coussy, Cyrille Chavet: Introduction de la prédiction de branchement dans la synthèse de haut niveau. Technique et Science Informatiques 32(2): 281-301 (2013)- [c22]Aroua Briki, Cyrille Chavet, Philippe Coussy: A memory mapping approach for network and controller optimization in parallel interleaver architectures. ACM Great Lakes Symposium on VLSI 2013: 321-322
- 2012
- [j8]Deming Chen, Kiyoung Choi, Philippe Coussy, Yuan Xie, Zhiru Zhang: ESL Design Methodology. J. Electrical and Computer Engineering 2012 (2012)
- [c21]Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini: OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. DSD 2012: 751-758
- [c20]Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin: A design approach dedicated to network-based and conflict-free parallel interleavers. ACM Great Lakes Symposium on VLSI 2012: 153-158
- [c19]Oscar Sanchez, Michel Jézéquel, Saeed ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy, Christophe Jégo: A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. SiPS 2012: 288-293
- 2011
- [c18]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin: A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP 2011: 1613-1616
- [c17]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin: An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS 2011: 1720-1723
- 2010
- [j7]Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet: High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1736-1749 (2010)
- [c16]Philippe Coussy, Andrés Takach, Michael McNamara, Mike Meredith: An introduction to the SystemC synthesis subset standard. CODES+ISSS 2010: 183-184
- [c15]Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin: Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA. FPL 2010: 464-468
- [c14]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin: Static Address Generation Easing: a design methodology for parallel interleaver architectures. ICASSP 2010: 1594-1597
- [c13]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin: Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS 2010: 466-469
- [c12]Ghizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin: Bitwidth-aware high-level synthesis for designing low-power DSP applications. ICECS 2010: 531-534
- [c11]Cyrille Chavet, Philippe Coussy: A memory mapping approach for parallel interleaver design with multiples read and write accesses. ISCAS 2010: 3168-3171
- [c10]Vincent Lefftz, Jean Bertrand, Hugues Cassé, Christophe Clienti, Philippe Coussy, Laurent Maillet-Contoz, Philippe Mercier, Pierre Moreau, Laurence Pierre, Emmanuel Vaumorin: A Design Flow for Critical Embedded Systems. SIES 2010: 229-233
- [i7]Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard: Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures. CoRR abs/1002.3990 (2010)
2000 – 2009
- 2009
- [j6]Philippe Coussy, Andrés Takach: Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design. IEEE Design & Test of Computers 26(4): 4-6 (2009)
- [j5]Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andrés Takach: An Introduction to High-Level Synthesis. IEEE Design & Test of Computers 26(4): 8-17 (2009)
- [j4]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin: Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. Signal Processing Systems 56(2-3): 167-186 (2009)
- 2008
- [j3]Philippe Coussy, Ghizlane Lhairech-Lebreton, Dominique Heller: Multiple Word-Length High-Level Synthesis. EURASIP J. Emb. Sys. 2008 (2008)
- 2007
- [j2]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin: Constrained algorithmic IP design for system-on-chip. Integration 40(2): 94-105 (2007)
- [c9]Caaliph Andriamisaina, Emmanuel Casseau, Philippe Coussy: Synthesis of Multimode digital signal processing systems. AHS 2007: 318-325
- [c8]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin: A design methodology for space-time adapter. ACM Great Lakes Symposium on VLSI 2007: 347-352
- [c7]Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin: A design flow dedicated to multi-mode architectures for DSP applications. ICCAD 2007: 604-611
- [c6]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin: A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. ISCAS 2007: 2946-2949
- [i6]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin: A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. CoRR abs/0706.1692 (2007)
- [i5]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin: A Design Methodology for Space-Time Adapter. CoRR abs/0706.2732 (2007)
- [i4]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin: Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels. CoRR abs/0706.2824 (2007)
- [i3]Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin: Application of a design space exploration tool to enhance interleaver generation. CoRR abs/0706.3009 (2007)
- 2006
- [j1]Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin: A formal method for hardware IP design and integration under I/O and timing constraints. ACM Trans. Embedded Comput. Syst. 5(1): 29-53 (2006)
- [c5]Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin: Design Space Exploration of DSP Applications Based on Behavioral Description Models. SiPS 2006: 244-249
- [i2]Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin: High-level synthesis under I/O Timing and Memory constraints. CoRR abs/cs/0605143 (2006)
- [i1]Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin: Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI. CoRR abs/cs/0605146 (2006)
- 2005
- [c4]L. Kriaa, S. Adriano, Emmanuel Vaumorin, R. Nouacer, F. Blanc, S. Pajaniardja, Philippe Coussy, Eric Martin, Dominique Heller, Farhat Thabet, Anne-Marie Fouilliart: SystemCmantic: A high level Modelling and Co-Design Framework. FDL 2005: 341-353
- [c3]Philippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin: High-level synthesis under I/O timing and memory constraints. ISCAS (1) 2005: 680-683
- 2003
- [c2]Philippe Coussy, Adel Baganne, Eric Martin: Communication and Timing Constraints Analysis for IP Design and Integration. VLSI-SOC 2003: 38-43
- 2002
- [c1]Philippe Coussy, Adel Baganne, Eric Martin: A design methodology for IP integration. ISCAS (4) 2002: 711-714
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-06-06 20:11 CEST by the dblp team