K. Wayne Current

Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija: Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. IEEE Trans. on Circuits and Systems 55-I(10): 3038-3049 (2008)

K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews: A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System. IEEE Trans. Biomed. Circuits and Systems 1(2): 105-115 (2007)

K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews: A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor. ICMENS 2005: 153-158

Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija: A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS 2005: 724-732

Yongjian Brandon Guo, K. Wayne Current: Voltage Comparator Circuits for Multiple-Valued CMOS Logic. ISMVL 2002: 67-

Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current: Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans. VLSI Syst. 8(4): 460-463 (2000)

Dan Olson, K. Wayne Current: Hardware Implementation of ``Supplementary Symmetrical Logic Circuit Structure'' Concepts. ISMVL 2000: 371-376

K. Wayne Current: Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. ISMVL 2000: 377-381

Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current: Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. ISLPED 1997: 323-327

K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic: Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. ISMVL 1996: 86-

K. Wayne Current: Memory Circuits for Multiple-Valued Logic Voltage Signals. ISMVL 1995: 52-57

Wei-Shang Chu, K. Wayne Current: Quaternary Multiplier Circuit. ISMVL 1994: 15-18

K. Wayne Current, Jim Parker, Wes Hardaker: Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs. ISCAS 1993: 2090-2093

K. Wayne Current: Multiple Valued Logic: Current-Mode CMOS Circuits. ISMVL 1993: 176-181

Eric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi: High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture. IEEE Trans. Circuits Syst. Video Techn. 2(4): 347-360 (1992)

K. Wayne Current: A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit. ISMVL 1992: 229-234

K. Wayne Current, M. E. Hurlston: A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit. ISMVL 1991: 196-202

K. Wayne Current, Paul J. Hurst, Eric Shieh, Iskender Agi: An evaluation of Radon transform computations using DSP chips. Mach. Vis. Appl. 3(2): 63-74 (1990)

K. Wayne Current: A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. ISMVL 1990: 168-173

James M. Apffel, K. Wayne Current, Jorge L. C. Sanz, Anil K. Jain: An architecture for region boundary extraction in raster scan images suitable for VLSI implementation. Mach. Vis. Appl. 2(4): 193-214 (1989)

James L. Mangin, K. Wayne Current: Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits. IEEE Trans. Computers 35(2): 157-161 (1986)

K. Wayne Current: High Density Integrated Computing Circuitry with Multiple Valued Logic. IEEE Trans. Computers 29(2): 191-195 (1980)

K. Wayne Current: Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders. IEEE Trans. Computers 29(5): 400-403 (1980)

K. Wayne Current: A High Data-Rate Digital Output Correlator Design. IEEE Trans. Computers 29(5): 403-405 (1980)

K. Wayne Current, Douglas A. Mow: Implementing Parallel Counters with Four-Valued Threshold Logic. IEEE Trans. Computers 28(3): 200-204 (1979)