Mehdi Dehbashi

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	2013
j1		Mehdi Dehbashi, André Sülflow, Görschwin Fey: Automated design debugging in a testbench-based verification environment. Microprocessors and Microsystems - Embedded Hardware Design 37(2): 206-217 (2013)
	2012
c7		Mehdi Dehbashi, Görschwin Fey: Automated Post-Silicon Debugging of Failing Speedpaths. Asian Test Symposium 2012: 13-18
c6		Mehdi Dehbashi, Görschwin Fey: Automated debugging from pre-silicon to post-silicon. DDECS 2012: 324-329
c5		Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan: On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD 2012: 431-436
c4		Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan: Functional analysis of circuits under timing variations. European Test Symposium 2012: 1
	2011
c3		Mehdi Dehbashi, André Sülflow, Görschwin Fey: Automated Design Debugging in a Testbench-Based Verification Environment. DSD 2011: 479-486
	2008
c2		Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi: Fault Effects in FlexRay-Based Networks with Hybrid Topology. ARES 2008: 491-496
	2007
c1		Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand: Assessment of Message Missing Failures in FlexRay-Based Networks. PRDC 2007: 191-194

Coauthor Index

1	Navid Farazmand	[c1]
2	Görschwin Fey	[j1] [c7] [c6] [c5] [c4] [c3]
3	Vahid Lari	[c2] [c1]
4	Seyed Ghassem Miremadi	[c2] [c1]
5	Anand Raghunathan	[c5] [c4]
6	Kaushik Roy	[c5] [c4]
7	Mohammad Shokrollah-Shirazi	[c2]
8	André Sülflow	[j1] [c3]

Last update Sat May 25 04:13:33 2013 CET by the DBLP Team —

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