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Madhav P. Desai
2010 – today
- 2010
[c23]Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai: A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems. DSD 2010: 147-154- [c22]Gautam Hazari, Madhav P. Desai, G. Srinivas: Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems. VLSI Design 2010: 15-20
- [i1]
2000 – 2009
- 2009
- [c21]Pratyush Kumar, Madhav P. Desai: Learning based address mapping for improving the performance of memory subsystems. MASCOTS 2009: 1-9
- 2007
- [c20]Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai: AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs. VLSI Design 2007: 245-250
- [c19]Gautam Hazari, Madhav P. Desai, H. Kasture: On the Impact of Address Space Assignment on Performance in Systems-on-Chip. VLSI Design 2007: 540-545
- [c18]Gaurav Trivedi, Madhav P. Desai, H. Narayanan: Parallelization of DC Analysis through Multiport Decomposition. VLSI Design 2007: 863-868
- 2006
- [c17]Gaurav Trivedi, Madhav P. Desai, H. Narayanan: Fast DC Analysis and Its Application to Combinatorial Optimization Problems. VLSI Design 2006: 695-700
- 2005
- [c16]Shabbir H. Batterywala, Madhav P. Desai: Variance Reduction in Monte Carlo Capacitance Extraction. VLSI Design 2005: 85-90
- [c15]Madhav P. Desai, D. Manjunath: On Range Matrices and Wireless Networks in d Dimensions. WiOpt 2005: 190-196
- 2004
- [c14]Vani Prasad, Madhav P. Desai: On Buffering Schemes for Long Multi-Layer Nets. VLSI Design 2004: 455-
- [c13]Gautam Hazari, Madhav P. Desai, Apoorv Gupta, Supratik Chakraborty: A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits. VLSI Design 2004: 565-570
- [c12]Aditya Mittal, Madhav P. Desai: A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator. VLSI Design 2004: 571-
- 2003
- [j3]Madhav P. Desai, H. Narayanan, Sachin B. Patkar: The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. Discrete Applied Mathematics 131(2): 299-310 (2003)
- [c11]Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao: Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. VLSI Design 2003: 99-104
- [c10]Vani Prasad, Madhav P. Desai: Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy. VLSI Design 2003: 417-422
- 2002
- [j2]Madhav P. Desai, D. Manjunath: On the connectivity in finite ad hoc networks. IEEE Communications Letters 6(10): 437-439 (2002)
- [c9]Maryam Shojaei Baghini, Madhav P. Desai: Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. VLSI Design 2002: 317-
- 2001
- [j1]Nihar R. Mohapatra, A. Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao: Sub-100 nm CMOS circuit performance with high-K gate dielectrics. Microelectronics Reliability 41(7): 1045-1048 (2001)
- [c8]Nihar R. Mohapatra, A. Dutta, Madhav P. Desai, V. Ramgopal Rao: Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. VLSI Design 2001: 479-
- [c7]Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai: An On-Chip Coupling Capacitance Measurement Technique. VLSI Design 2001: 495-499
- 2000
- [c6]Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal: Inductance Characterization of Small Interconnects Using Test-Signal Method. VLSI Design 2000: 376-
1990 – 1999
- 1999
- [c5]Rupesh S. Shelar, Madhav P. Desai, H. Narayanan: Decomposition of Finite State Machines for Area, Delay Minimization. ICCD 1999: 620-625
- [c4]B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai: A State Assignment Scheme Targeting Performance and Area. VLSI Design 1999: 378-383
- 1998
- [c3]Nevine Nassif, Madhav P. Desai, Dale H. Hall: Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. DAC 1998: 230-235
- 1996
- [c2]Madhav P. Desai, Yao-Tsung Yen: A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation. DAC 1996: 125-130
- [c1]Madhav P. Desai, Radenko Cvijetic, James Jensen: Sizing of Clock Distribution Networks for High Performance CPU Chips. DAC 1996: 389-394
Coauthor Index
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last updated on 2012-12-02 22:04 CET by the dblp team