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 | 2013 | |
|---|---|---|
| j81 |      | Michel A. Kinsy, Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, G. Edward Suh, Srinivas Devadas: Optimal and Heuristic Application-Aware Oblivious Routing. IEEE Trans. Computers 62(1): 59-73 (2013) |
| c118 | | Michel A. Kinsy, Ivan Celanovic, Omer Khan, Srinivas Devadas: MARTHA: architecture for control and emulation of power electronics and smart grid systems. DATE 2013: 519-524 |
| c117 | | Michel A. Kinsy, Michael Pellauer, Srinivas Devadas: Heracles: a tool for fast RTL-based design space exploration of multicore processors. FPGA 2013: 125-134 |
| i6 | | Ling Ren, Xiangyao Yu, Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas: Design Space Exploration and Optimization of Path Oblivious RAM in Secure Processors. IACR Cryptology ePrint Archive 2013: 76 (2013) |
| i5 | | Ulrich Rührmair, Jan Sölter, Frank Sehnke, Xiaolin Xu, Ahmed Mahmoud, Vera Stoyanova, Gideon Dror, Jürgen Schmidhuber, Wayne Burleson, Srinivas Devadas: PUF Modeling Attacks on Simulated and Silicon Data. IACR Cryptology ePrint Archive 2013: 112 (2013) |
| 2012 | ||
| j80 | | Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas: HORNET: A Cycle-Level Multicore Simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 31(6): 890-903 (2012) |
| j79 | | Henry Hoffmann, Anant Agarwal, Srinivas Devadas: Selecting Spatiotemporal Patterns for Development of Parallel Applications. IEEE Trans. Parallel Distrib. Syst. 23(10): 1970-1982 (2012) |
| c116 | | Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas: A low-overhead dynamic optimization framework for multicores. PACT 2012: 467-468 |
| c115 | | Henry Hoffmann, Jim Holt, George Kurian, Eric Lau, Martina Maggio, Jason E. Miller, Sabrina M. Neuman, Mahmut E. Sinangil, Yildiz Sinangil, Anant Agarwal, Anantha P. Chandrakasan, Srinivas Devadas: Self-aware computing in the Angstrom processor. DAC 2012: 259-264 |
| c114 | | Meng-Day (Mandel) Yu, Richard Sowell, Alok Singh, David M'Raïhi, Srinivas Devadas: Performance metrics and empirical results of a PUF cryptographic key generation ASIC. HOST 2012: 108-115 |
| c113 | | Vijay Ganesh, Charles W. O'Donnell, Mate Soos, Srinivas Devadas, Martin C. Rinard, Armando Solar-Lezama: Lynx: A Programmatic SAT Solver for the RNA-Folding Problem. SAT 2012: 143-156 |
| c112 | | Mehrdad Majzoobi, Masoud Rostami, Farinaz Koushanfar, Dan S. Wallach, Srinivas Devadas: Slender PUF Protocol: A Lightweight, Robust, and Secure Authentication by Substring Matching. IEEE Symposium on Security and Privacy Workshops 2012: 33-44 |
| i4 | | Christopher W. Fletcher, Marten van Dijk, Srinivas Devadas: Compilation Techniques for Efficient Encrypted Computation. IACR Cryptology ePrint Archive 2012: 266 (2012) |
| 2011 | ||
| j78 | | Charles W. O'Donnell, Jérôme Waldispühl, Mieszko Lis, Randal Halfmann, Srinivas Devadas, Susan Lindquist, Bonnie Berger: A method for probing the mutational landscape of amyloid structure. Bioinformatics [ISMB/ECCB] 27(13): 34-42 (2011) |
| j77 | | Omer Khan, Mieszko Lis, Yildiz Sinangil, Srinivas Devadas: DCC: A Dependable Cache Coherence Multicore Architecture. Computer Architecture Letters 10(1): 12-15 (2011) |
| j76 | | Solomon Shenker, Charles W. O'Donnell, Srinivas Devadas, Bonnie Berger, Jérôme Waldispühl: Efficient Traversal of Beta-Sheet Protein Folding Pathways Using Ensemble Models. Journal of Computational Biology 18(11): 1635-1647 (2011) |
| c111 | | Mehrdad Majzoobi, Farinaz Koushanfar, Srinivas Devadas: FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control. CHES 2011: 17-32 |
| c110 | | Meng-Day (Mandel) Yu, David M'Raïhi, Richard Sowell, Srinivas Devadas: Lightweight and Secure PUF Key Storage Using Limits of Machine Learning. CHES 2011: 358-373 |
| c109 | | Michel A. Kinsy, Michael Pellauer, Srinivas Devadas: Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System. FPL 2011: 356-362 |
| c108 | | Victor Costan, Srinivas Devadas: Security challenges and opportunities in adaptive and reconfigurable hardware. HOST 2011: 1-5 |
| c107 | | Zdenek Sid Paral, Srinivas Devadas: Reliable and efficient PUF-based key generation using pattern matching. HOST 2011: 128-133 |
| c106 | | Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Srinivas Devadas: Memory coherence in the age of multicores. ICCD 2011: 1-8 |
| c105 | | Omer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas: ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores. ICCD 2011: 411-418 |
| c104 | | Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas: Scalable, accurate multicore simulation in the 1000-core era. ISPASS 2011: 175-185 |
| c103 | | Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas: Deadlock-free fine-grained thread migration. NOCS 2011: 33-40 |
| c102 | | Solomon Shenker, Charles W. O'Donnell, Srinivas Devadas, Bonnie Berger, Jérôme Waldispühl: Efficient Traversal of Beta-Sheet Protein Folding Pathways Using Ensemble Models. RECOMB 2011: 408-423 |
| c101 | | Michel A. Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola L. Celanovic, Srinivas Devadas: Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems. RTSS 2011: 305-316 |
| c100 | | Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Christopher W. Fletcher, Michel A. Kinsy, Ilia A. Lebedev, Omer Khan, Srinivas Devadas: Brief announcement: distributed shared memory based on computation migration. SPAA 2011: 253-256 |
| 2010 | ||
| j75 | | Meng-Day (Mandel) Yu, Srinivas Devadas: Secure and Robust Error Correction for Physical Unclonable Functions. IEEE Design & Test of Computers 27(1): 48-65 (2010) |
| c99 | | Ulrich Rührmair, Frank Sehnke, Jan Sölter, Gideon Dror, Srinivas Devadas, Jürgen Schmidhuber: Modeling attacks on physical unclonable functions. ACM Conference on Computer and Communications Security 2010: 237-249 |
| i3 | | Ulrich Rührmair, Frank Sehnke, Jan Sölter, Gideon Dror, Srinivas Devadas, Jürgen Schmidhuber: Modeling Attacks on Physical Unclonable Functions. IACR Cryptology ePrint Archive 2010: 251 (2010) |
| 2009 | ||
| j74 | | Mieszko Lis, Maxim N. Artyomov, Srinivas Devadas, Arup K. Chakraborty: Efficient stochastic simulation of reaction-diffusion processes via direct compilation. Bioinformatics 25(17): 2289-2291 (2009) |
| j73 | | Jérôme Waldispühl, Srinivas Devadas, Bonnie Berger, Peter Clote: RNAmutants: a web server to explore the mutational landscape of RNA secondary structures. Nucleic Acids Research 37(Web-Server-Issue): 281-286 (2009) |
| c98 | | Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel A. Kinsy, Tina Wen, Srinivas Devadas: Oblivious Routing in On-Chip Bandwidth-Adaptive Networks. PACT 2009: 181-190 |
| c97 | | Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edward Suh, Marten van Dijk, Srinivas Devadas: Application-aware deadlock-free oblivious routing. ISCA 2009: 208-219 |
| c96 | | Keun Sup Shim, Myong Hyon Cho, Michel A. Kinsy, Tina Wen, Mieszko Lis, G. Edward Suh, Srinivas Devadas: Static virtual channel allocation in oblivious routing. NOCS 2009: 38-43 |
| c95 | | Jérôme Waldispühl, Charles W. O'Donnell, Sebastian Will, Srinivas Devadas, Rolf Backofen, Bonnie Berger: Simultaneous Alignment and Folding of Protein Sequences. RECOMB 2009: 339-355 |
| 2008 | ||
| j72 | | Jérôme Waldispühl, Srinivas Devadas, Bonnie Berger, Peter Clote: Efficient Algorithms for Probing the RNA Mutation Landscape. PLoS Computational Biology 4(8) (2008) |
| j71 | | Blaise Gassend, Marten van Dijk, Dwaine E. Clarke, Emina Torlak, Srinivas Devadas, Pim Tuyls: Controlled physical random functions and applications. ACM Trans. Inf. Syst. Secur. 10(4) (2008) |
| c94 | | Victor Costan, Luis F. G. Sarmenta, Marten van Dijk, Srinivas Devadas: The Trusted Execution Module: Commodity General-Purpose Trusted Computing. CARDIS 2008: 133-148 |
| c93 | | Myong Hyon Cho, Chih-Chi Cheng, Michel A. Kinsy, G. Edward Suh, Srinivas Devadas: Diastolic arrays: throughput-driven reconfigurable computing. ICCAD 2008: 457-464 |
| c92 | | Luis F. G. Sarmenta, Marten van Dijk, Jonathan Rhodes, Srinivas Devadas: Offline count-limited certificates. SAC 2008: 2145-2152 |
| 2007 | ||
| j70 | | Blaise Gassend, Charles W. O'Donnell, William Thies, Andrew Lee, Marten van Dijk, Srinivas Devadas: Learning biophysically-motivated parameters for alpha helix prediction. BMC Bioinformatics 8(S-5) (2007) |
| j69 | | G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas: Aegis: A Single-Chip Secure Processor. IEEE Design & Test of Computers 24(6): 570-580 (2007) |
| c91 | | Marten van Dijk, Jonathan Rhodes, Luis F. G. Sarmenta, Srinivas Devadas: Offline untrusted storage with immediate detection of forking and replay attacks. STC 2007: 41-48 |
| c90 | | G. Edward Suh, Srinivas Devadas: Physical Unclonable Functions for Device Authentication and Secret Key Generation. DAC 2007: 9-14 |
| 2006 | ||
| j68 | | Marten van Dijk, Dwaine E. Clarke, Blaise Gassend, G. Edward Suh, Srinivas Devadas: Speeding up Exponentiation using an Untrusted Computational Resource. Des. Codes Cryptography 39(2): 253-273 (2006) |
| c89 | | Luis F. G. Sarmenta, Marten van Dijk, Charles W. O'Donnell, Jonathan Rhodes, Srinivas Devadas: Virtual monotonic counters and count-limited objects using a TPM without a trusted OS. STC 2006: 27-42 |
| c88 | | Blaise Gassend, Charles W. O'Donnell, William Thies, Andrew Lee, Marten van Dijk, Srinivas Devadas: Predicting Secondary Structure of All-Helical Proteins Using Hidden Markov Support Vector Machines. PRIB 2006: 93-104 |
| i2 | | Marten van Dijk, Emina Torlak, Blaise Gassend, Srinivas Devadas: A Generalized Two-Phase Analysis of Knowledge Flows in Security Protocols. CoRR abs/cs/0605097 (2006) |
| i1 | | Emina Torlak, Marten van Dijk, Blaise Gassend, Daniel Jackson, Srinivas Devadas: Knowledge Flow Analysis for Security Protocols. CoRR abs/cs/0605109 (2006) |
| 2005 | ||
| j67 | | G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas: AEGIS: A single-chip secure processor. Inf. Sec. Techn. Report 10(2): 63-73 (2005) |
| j66 | | Daihyun Lim, Jae W. Lee, Blaise Gassend, G. Edward Suh, Marten van Dijk, Srinivas Devadas: Extracting secret keys from integrated circuits. IEEE Trans. VLSI Syst. 13(10): 1200-1205 (2005) |
| c87 | | G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas: Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions. ISCA 2005: 25-36 |
| c86 | | Dwaine E. Clarke, G. Edward Suh, Blaise Gassend, Ajay Sudan, Marten van Dijk, Srinivas Devadas: Towards Constant Bandwidth Overhead Integrity Checking of Untrusted Data. IEEE Symposium on Security and Privacy 2005: 139-153 |
| 2004 | ||
| j65 | | Blaise Gassend, Daihyun Lim, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas: Identification and authentication of integrated circuits. Concurrency - Practice and Experience 16(11): 1077-1098 (2004) |
| j64 | | Sanjay Raman, Dwaine E. Clarke, Matt Burnside, Srinivas Devadas, Ronald L. Rivest: Access-controlled resource discovery in pervasive networks. Concurrency - Practice and Experience 16(11): 1099-1120 (2004) |
| j63 | | José C. Costa, Luis Miguel Silveira, Srinivas Devadas, José Monteiro: Power Estimation Using Probability Polynomials. Design Autom. for Emb. Sys. 9(1): 19-52 (2004) |
| j62 | | G. Edward Suh, Larry Rudolph, Srinivas Devadas: Dynamic Partitioning of Shared Cache Memory. The Journal of Supercomputing 28(1): 7-26 (2004) |
| c85 | | G. Edward Suh, Jae W. Lee, David Zhang, Srinivas Devadas: Secure program execution via dynamic information flow tracking. ASPLOS 2004: 85-96 |
| c84 | | Hari Balakrishnan, Srinivas Devadas, Douglas Ehlert, Arvind: Rate Guarantees and Overload Protection in Input-Queued Switches. INFOCOM 2004 |
| 2003 | ||
| j61 | | George Hadjiyiannis, Srinivas Devadas: Techniques for accurate performance evaluation in architecture exploration. IEEE Trans. VLSI Syst. 11(4): 601-615 (2003) |
| c83 | | Dwaine E. Clarke, Srinivas Devadas, Marten van Dijk, Blaise Gassend, G. Edward Suh: Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking. ASIACRYPT 2003: 188-207 |
| c82 | | |
| c81 | | Blaise Gassend, G. Edward Suh, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas: Caches and Hash Trees for Efficient Memory Integrity Verification. HPCA 2003: 295-306 |
| c80 | | G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas: AEGIS: architecture for tamper-evident and tamper-resistant processing. ICS 2003: 160-171 |
| c79 | | G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas: Efficient Memory Integrity Verification and Encryption for Secure Processors. MICRO 2003: 339-350 |
| c78 |  | Blaise Gassend, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas: Delay-Based Circuit Authentication and Applications. SAC 2003: 294-301 |
| c77 | | Sanjay Raman, Dwaine E. Clarke, Matt Burnside, Srinivas Devadas, Ronald L. Rivest: Access-Controlled Resource Discovery for Pervasive Networks. SAC 2003: 338-345 |
| 2002 | ||
| j60 | | Farzan Fallah, Pranav Ashar, Srinivas Devadas: Functional vector generation for sequential HDL models under an observability-based code coverage metric. IEEE Trans. VLSI Syst. 10(6): 919-923 (2002) |
| c76 | | Blaise Gassend, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas: Controlled Physical Random Functions. ACSAC 2002: 149-160 |
| c75 | | Blaise Gassend, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas: Silicon physical random functions. ACM Conference on Computer and Communications Security 2002: 148-160 |
| c74 | | G. Edward Suh, Srinivas Devadas, Larry Rudolph: A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. HPCA 2002: 117-128 |
| c73 | | Dwaine E. Clarke, Blaise Gassend, Thomas Kotwal, Matt Burnside, Marten van Dijk, Srinivas Devadas, Ronald L. Rivest: The Untrusted Computer Problem and Camera-Based Authentication. Pervasive 2002: 114-124 |
| c72 | | Matt Burnside, Dwaine E. Clarke, Todd Mills, Andrew Maywah, Srinivas Devadas, Ronald L. Rivest: Proxy-based security protocols in networked mobile devices. SAC 2002: 265-272 |
| e2 | | Peter Marwedel, Srinivas Devadas (Eds.): Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002. ACM 2002, isbn 1-58113-527-0 |
| 2001 | ||
| j59 | | Farzan Fallah, Srinivas Devadas, Kurt Keutzer: Functional vector generation for HDL models using linearprogramming and Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 20(8): 994-1002 (2001) |
| j58 | | Farzan Fallah, Srinivas Devadas, Kurt Keutzer: OCCOM-efficient computation of observability-based code coveragemetrics for functional verification. IEEE Trans. on CAD of Integrated Circuits and Systems 20(8): 1003-1015 (2001) |
| c71 | | Prabhat Jain, Srinivas Devadas, Daniel W. Engels, Larry Rudolph: Software-Assisted Cache Replacement Mechanisms for Embedded Systems. ICCAD 2001: 119-126 |
| c70 | | G. Edward Suh, Srinivas Devadas, Larry Rudolph: Analytical cache models with applications to cache partitioning. ICS 2001: 1-12 |
| c69 | | G. Edward Suh, Larry Rudolph, Srinivas Devadas: Effects of Memory Performance on Parallel Job Scheduling. JSSPP 2001: 116-132 |
| 2000 | ||
| j57 | | George Hadjiyiannis, Silvina Hanono, Srinivas Devadas: ISDL: An Instruction Set Description Language for Retargetability and Architecture Exploration. Design Autom. for Emb. Sys. 6(1): 39-69 (2000) |
| j56 | | Farzan Fallah, Stan Y. Liao, Srinivas Devadas: Solving covering problems using LPR-based lower bounds. IEEE Trans. VLSI Syst. 8(1): 9-17 (2000) |
| c68 | | Derek Chiou, Prabhat Jain, Larry Rudolph, Srinivas Devadas: Application-specific memory management for embedded systems using software-controlled caches. DAC 2000: 416-419 |
| c67 | | José C. Costa, Srinivas Devadas, José Monteiro: Observability Analysis of Embedded Software for Coverage-Directed Validation. ICCAD 2000: 27-32 |
| e1 | | L. Miguel Silveira, Srinivas Devadas, Ricardo Augusto da Luz Reis (Eds.): VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), December 1-4, 1999, Lisbon, Portugal. IFIP Conference Proceedings 162, Kluwer 2000, isbn 0-7923-7731-1 |
| 1999 | ||
| j55 | | Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas: Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures. Design Autom. for Emb. Sys. 4(1): 5-22 (1999) |
| j54 | | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer: A text-compression-based method for code size minimization in embedded systems. ACM Trans. Design Autom. Electr. Syst. 4(1): 12-38 (1999) |
| c66 | | Farzan Fallah, Pranav Ashar, Srinivas Devadas: Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. DAC 1999: 666-671 |
| c65 | | George Hadjiyiannis, Pietro Russo, Srinivas Devadas: A Methodology for Accurate Performance Evaluation in Architecture Exploration. DAC 1999: 927-932 |
| c64 | | Srinivas Devadas, Sharad Malik, José C. Monteiro, Luciano Lavagno: CAD Techniques for Embedded System Design. VLSI Design 1999: 608 |
| 1998 | ||
| j53 | | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Code Optimization Techniques in Embedded DSP Microprocessors. Design Autom. for Emb. Sys. 3(1): 59-73 (1998) |
| j52 | | José C. Monteiro, Srinivas Devadas, Abhijit Ghosh: Sequential logic optimization for low power using input-disabling precomputation architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 279-284 (1998) |
| j51 | | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer: Code density optimization for embedded DSP processors using data compression techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 17(7): 601-608 (1998) |
| j50 | | Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas: BDD-based synthesis of extended burst-mode controllers. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 782-792 (1998) |
| j49 | | Stan Y. Liao, Kurt Keutzer, Steven W. K. Tjiang, Srinivas Devadas: A new viewpoint on code generation for directed acyclic graphs. ACM Trans. Design Autom. Electr. Syst. 3(1): 51-75 (1998) |
| j48 | | George Hadjiyiannis, Anantha Chandrakasan, Srinivas Devadas: A low power, low bandwidth protocol for remote wireless terminals. Wireless Networks 4(1): 3-15 (1998) |
| c63 | | Farzan Fallah, Srinivas Devadas, Kurt Keutzer: OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification. DAC 1998: 152-157 |
| c62 | | Silvina Hanono, Srinivas Devadas: Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. DAC 1998: 510-515 |
| c61 | | Farzan Fallah, Srinivas Devadas, Kurt Keutzer: Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. DAC 1998: 528-533 |
| c60 | | Srinivas Devadas, Kurt Keutzer: An algorithmic approach to optimizing fault coverage for BIST logic synthesis. ITC 1998: 164-173 |
| 1997 | ||
| j47 | | José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White: Estimation of average switching activity in combinational logic circuits using symbolic simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 121-127 (1997) |
| c59 | | Stan Y. Liao, Srinivas Devadas: Solving Covering Problems Using LPR-Based Lower Bounds. DAC 1997: 117-120 |
| c58 | | Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas: Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures. DAC 1997: 287-292 |
| c57 | | George Hadjiyiannis, Silvina Hanono, Srinivas Devadas: ISDL: An Instruction Set Description Language for Retargetability. DAC 1997: 299-302 |
| c56 | | José C. Costa, José C. Monteiro, Srinivas Devadas: Switching activity estimation using limited depth reconvergent path analysis. ISLPED 1997: 184-189 |
| 1996 | ||
| j46 | | Srinivas Devadas, Kurt Keutzer: Addendum to "Synthesis of robust delay-fault testable circuits: Theory". IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 445-446 (1996) |
| j45 | | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Storage Assignment to Decrease Code Size. ACM Trans. Program. Lang. Syst. 18(3): 235-253 (1996) |
| j44 | | Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin: Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. IEEE Trans. VLSI Syst. 4(4): 495 (1996) |
| j43 | | José Monteiro, Srinivas Devadas: Techniques for power estimation and optimization at the logic level: A survey. VLSI Signal Processing 13(2-3): 259-276 (1996) |
| c55 | | José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar: Scheduling Techniques to Enable Power Management. DAC 1996: 349-352 |
| c54 | | Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer: An observability-based code coverage metric for functional simulation. ICCAD 1996: 418-425 |
| 1995 | ||
| j42 | | Amelia Shen, Srinivas Devadas, Abhijit Ghosh: Probabilistic manipulation of Boolean functions using free Boolean diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 87-95 (1995) |
| j41 | | Bill Lin, Srinivas Devadas: Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 974-985 (1995) |
| j40 | | Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin: Power estimation methods for sequential logic circuits. IEEE Trans. VLSI Syst. 3(3): 404-416 (1995) |
| c53 | | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer: Code density optimization for embedded DSP processors using data compression techniques. ARVLSI 1995: 272-285 |
| c52 | | José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh: Optimization of combinational and sequential logic circuits for low power using precomputation. ARVLSI 1995: 430-444 |
| c51 | | Srinivas Devadas, Sharad Malik: A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. DAC 1995: 242-247 |
| c50 | | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Code Optimization Techniques for Embedded DSP Microprocessors. DAC 1995: 599-604 |
| c49 | | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang: Instruction selection using binate covering for code size optimization. ICCAD 1995: 393-399 |
| c48 | | José Monteiro, Srinivas Devadas: Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs. ISLPD 1995: 33-38 |
| c47 | | Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Storage Assignment to Decrease Code Size. PLDI 1995: 186-195 |
| 1994 | ||
| j39 | | Filip Van Aelten, Jonathan Allen, Srinivas Devadas: Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 122-134 (1994) |
| j38 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 814-822 (1994) |
| j37 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Certified timing verification and the transition delay of a logic circuit. IEEE Trans. VLSI Syst. 2(3): 333-342 (1994) |
| j36 | | Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. IEEE Trans. VLSI Syst. 2(4): 426-436 (1994) |
| j35 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Verification of asynchronous interface circuits with bounded wire delays. VLSI Signal Processing 7(1-2): 161-182 (1994) |
| c46 | | José C. Monteiro, Srinivas Devadas, Bill Lin: A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. DAC 1994: 12-17 |
| c45 | | Vishal Bhagwati, Srinivas Devadas: Automatic Verification of Pipelined Microprocessors. DAC 1994: 603-608 |
| c44 | | Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert Wang: Challenges in code generation for embedded processors. Code Generation for Embedded Processors 1994: 48-64 |
| c43 | | Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. ICCAD 1994: 74-81 |
| c42 | | Bill Lin, Srinivas Devadas: Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. ICCAD 1994: 542-549 |
| c41 | | Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas: Performance-driven synthesis of asynchronous controllers. ICCAD 1994: 550-557 |
| c40 | | José C. Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto: Bitwise Encoding of Finite State Machines. VLSI Design 1994: 379-382 |
| 1993 | ||
| j34 | | |
| j33 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik: A synthesis-based test generation and compaction algorithm for multifaults. J. Electronic Testing 4(1): 91-104 (1993) |
| j32 | | Pranav Ashar, Srinivas Devadas, Kurt Keutzer: Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. Formal Methods in System Design 2(1): 93-112 (1993) |
| j31 | | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Sequential test generation and synthesis for testability at the register-transfer and logic levels. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 579-598 (1993) |
| j30 | | Srinivas Devadas: Comparing two-level and ordered binary decision diagram representations of logic functions. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 722-723 (1993) |
| j29 | | Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer: Delay-fault test generation and synthesis for testability under a standard scan design methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1217-1231 (1993) |
| j28 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik: Computation of floating mode delay in combinational circuits: theory and algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1913-1923 (1993) |
| j27 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1924-1936 (1993) |
| j26 | | Filip Van Aelten, Jonathan Allen, Srinivas Devadas: Verification of relations between synchronous machines. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1947-1959 (1993) |
| j25 | | Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer: Statistical timing analysis of combinational logic circuits. IEEE Trans. VLSI Syst. 1(2): 126-137 (1993) |
| c39 | | José C. Monteiro, Srinivas Devadas, Abhijit Ghosh: Retiming sequential circuits for low power. ICCAD 1993: 398-402 |
| c38 | | Amelia Shen, Srinivas Devadas, Abhijit Ghosh: Probabilistic construction and manipulation of free Boolean diagrams. ICCAD 1993: 544-583 |
| c37 | | Stan Y. Liao, Srinivas Devadas, Abhijit Ghosh: Boolean factorization using multiple-valued minimization. ICCAD 1993: 606-611 |
| 1992 | ||
| j24 | | Srinivas Devadas, Kurt Keutzer: Synthesis of robust delay-fault-testable circuits: theory. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 87-101 (1992) |
| j23 | | Srinivas Devadas, Kurt Keutzer: Synthesis of robust delay-fault-testable circuits: practice. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 277-300 (1992) |
| j22 | | Srinivas Devadas, Kurt Keutzer, Jacob K. White: Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 373-383 (1992) |
| j21 | | Michael J. Bryan, Srinivas Devadas, Kurt Keutzer: Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 800-803 (1992) |
| j20 | | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Heuristic minimization of Boolean relations using testing techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1166-1172 (1992) |
| j19 | | Srinivas Devadas, Kurt Keutzer: Validatable nonrobust delay-fault testable circuits via logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 11(12): 1559-1573 (1992) |
| c36 | | Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob White: Estimation of Average Switching Activity in Combinational and Sequential Circuits. DAC 1992: 253-259 |
| c35 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Certified Timing Verification and the Transition Delay of a Logic Circuit. DAC 1992: 549-555 |
| c34 | | Filip Van Aelten, Stan Y. Liao, Jonathan Allen, Srinivas Devadas: Automatic generation and verification of sufficient correctness properties for synchronous processors. ICCAD 1992: 183-187 |
| c33 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Verification of asynchronous interface circuits with bounded wire delays. ICCAD 1992: 188-195 |
| c32 | | Amelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer: On average power dissipation and random pattern testability of CMOS combinational logic networks. ICCAD 1992: 402-407 |
| c31 | | Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik: Statistical Timing Analysis of Combinational Circuits. ICCD 1992: 38-43 |
| 1991 | ||
| j18 | | Srinivas Devadas, A. Richard Newton: Exact algorithms for output encoding, state assignment, and four-level Boolean minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 13-27 (1991) |
| j17 | | Srinivas Devadas, Kurt Keutzer: A unified approach to the synthesis of fully testable sequential machines. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 39-50 (1991) |
| j16 | | Pranav Ashar, Srinivas Devadas, A. Richard Newton: Optimum and heuristic algorithms for an approach to finite state machine decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 296-310 (1991) |
| j15 | | Pranav Ashar, Srinivas Devadas, A. Richard Newton: Irredundant interacting sequential machines via optimal logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 311-325 (1991) |
| j14 | | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Test generation and verification for highly sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 652-667 (1991) |
| j13 | | Srinivas Devadas: Optimizing interacting finite state machines using sequential don't cares. IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1473-1484 (1991) |
| c30 | | Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer: Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology. DAC 1991: 80-86 |
| c29 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik: A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. DAC 1991: 359-365 |
| c28 | | Srinivas Devadas, Kurt Keutzer, Sharad Malik: Delay Computation in Combinational Logic Circuits: Theory and Algorithms. ICCAD 1991: 176-179 |
| c27 | | Filip Van Aelten, Jonathan Allen, Srinivas Devadas: Verification of Relations Between Synchronous Machines. ICCAD 1991: 380-383 |
| c26 | | James H. Kukula, Srinivas Devadas: Finite State Machine Decomposition by Transition Pairing. ICCAD 1991: 414-417 |
| c25 | | Srinivas Devadas, Kurt Keutzer, A. S. Krishnakumar: Design Verfication and Reachability Analysis Using Algebraic Manipulation. ICCD 1991: 250-258 |
| c24 | | Pranav Ashar, Abhijit Ghosh, Srinivas Devadas: Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. ICCD 1991: 259-264 |
| c23 | | Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer: A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits. ITC 1991: 403-410 |
| c22 | | Pranav Ashar, Srinivas Devadas, Kurt Keutzer: Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. ITC 1991: 887-896 |
| 1990 | ||
| j12 | | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton: Redundancies and don't cares in sequential logic synthesis. J. Electronic Testing 1(1): 15-30 (1990) |
| j11 | | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: Irredundant sequential machines via optimal logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 8-18 (1990) |
| j10 | | Srinivas Devadas, Hi-Keung Tony Ma: Easily testable PLA-based finite state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 9(6): 604-611 (1990) |
| c21 | | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Verification of Interacting Sequential Circuits. DAC 1990: 213-219 |
| c20 | | Srinivas Devadas, Kurt Keutzer: Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. DAC 1990: 221-227 |
| c19 | | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Sequential Test Generation at the Register-Transfer and Logic Levels. DAC 1990: 580-586 |
| c18 | | Pranav Ashar, Srinivas Devadas, A. Richard Newton: A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. DAC 1990: 601-606 |
| c17 | | Srinivas Devadas, Kurt Keutzer: An Automata-Theoretic Approach to Behavioral Equivalence. ICCAD 1990: 30-33 |
| c16 | | Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. ICCAD 1990: 84-87 |
| c15 | | Michael J. Bryan, Srinivas Devadas, Kurt Keutzer: Testability-Preserving Circuit Transformations. ICCAD 1990: 456-459 |
| c14 | | Srinivas Devadas: Minimization of Functions with Multiple-Valued Outputs: Theory and Applications. ISMVL 1990: 308-315 |
| c13 | | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton: Sequential logic synthesis for testability using register-transfer level descriptions. ITC 1990: 274-283 |
| c12 | | Srinivas Devadas, Kurt Keutzer: Design of integrated circuits fully testable for delay-faults and multifaults. ITC 1990: 284-293 |
| 1989 | ||
| j9 | | Hi-Keung Tony Ma, Srinivas Devadas, Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli: Logic verification algorithms and their parallel implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 181-189 (1989) |
| j8 | | Srinivas Devadas, A. Richard Newton: Algorithms for hardware allocation in data path synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 8(7): 768-781 (1989) |
| j7 | | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: A synthesis and optimization procedure for fully and easily testable sequential machines. IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1100-1107 (1989) |
| j6 | | Srinivas Devadas, A. Richard Newton: Decomposition and factorization of sequential finite state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 8(11): 1206-1217 (1989) |
| c11 | | |
| c10 | | Srinivas Devadas: General Decomposition of Sequential Machines: Relationships to State Assignment. DAC 1989: 314-320 |
| c9 | | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton: Easily testable PLA-based finite state machines. FTCS 1989: 102-109 |
| c8 | | |
| c7 | | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton: Redundancies and Don't Cares in Sequential Logic Synthesis. ITC 1989: 491-500 |
| 1988 | ||
| j5 | | Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma: Techniques for multilayer channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 698-712 (1988) |
| j4 | | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton: On the verification of sequential machines at differing levels of abstraction. IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 713-722 (1988) |
| j3 | | Hi-Keung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: Test generation for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1081-1093 (1988) |
| j2 | | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: MUSTANG: state assignment of finite state machines targeting multilevel logic implementations. IEEE Trans. on CAD of Integrated Circuits and Systems 7(12): 1290-1300 (1988) |
| c6 | | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines. ITC 1988: 621-630 |
| c5 | | Hi-Keung Tony Ma, A. Richard Newton, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli: An Incomplete Scan Design Approach to Test Generation for Sequential Machines. ITC 1988: 730-734 |
| 1987 | ||
| j1 | | Srinivas Devadas, A. Richard Newton: Topological Optimization of Multiple-Level Array Logic. IEEE Trans. on CAD of Integrated Circuits and Systems 6(6): 915-941 (1987) |
| c4 | | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton: On the Verification of Sequential Machines at Differing Levels of Abstraction. DAC 1987: 271-276 |
| c3 | | Hi-Keung Tony Ma, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli, R. Wei: Logic Verification Algorithms and Their Parallel Implementation. DAC 1987: 283-290 |
| 1986 | ||
| c2 | | Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli: Chameleon: a new multi-layer channel router. DAC 1986: 495-502 |
| c1 | | Srinivas Devadas, A. Richard Newton: GENIE: a generalized array optimizer for VLSI synthesis. DAC 1986: 631-637 |
Colors in the list of coauthors
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