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 | 2012 | |
|---|---|---|
| c16 |      | Artur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel: Embedded synthetic instruments for Board-Level testing. European Test Symposium 2012: 1 |
| c15 | | Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel: FPGA-based synthetic instrumentation for board test. ITC 2012: 1-10 |
| 2011 | ||
| j2 | | Eero Ivask, Sergei Devadze, Raimund Ubar: Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Computing: Practice and Experience 12(1) (2011) |
| c14 | | Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze: Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium 2011: 532-538 |
| c13 | | Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze: SoC and Board Modeling for Processor-Centric Board Testing. DSD 2011: 575-582 |
| c12 | | Artur Jutman, Sergei Devadze, Igor Aleksejev: Invited paper: System-wide fault management based on IEEE P1687 IJTAG. ReCoSoC 2011: 1-4 |
| 2010 | ||
| c11 | | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Parallel X-fault simulation with critical path tracing technique. DATE 2010: 879-884 |
| c10 | | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA 2010: 14-19 |
| c9 | | Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD 2010: 658-663 |
| c8 | | Anton Tsertov, Artur Jutman, Sergei Devadze: Testing beyond the SoCs in a lego style. EWDTS 2010: 334-338 |
| c7 | | Eero Ivask, Sergei Devadze, Raimund Ubar: Collaborative Distributed Fault Simulation for Digital Electronic Circuits. IDC 2010: 67-76 |
| c6 | | Eero Ivask, Sergei Devadze, Raimund Ubar: Collaborative Distributed Computing in the Field of Digital Electronics Testing. BASYS 2010: 145-152 |
| 2009 | ||
| c5 | | Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar: Fast extended test access via JTAG and FPGAs. ITC 2009: 1-7 |
| 2008 | ||
| c4 | | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Parallel fault backtracing for calculation of fault coverage. ASP-DAC 2008: 667-672 |
| c3 | | Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee: Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227 |
| 2007 | ||
| j1 | | Raimund Ubar, Artur Jutman, Margus Kruus, Elmet Orasson, Sergei Devadze, Heinz-Dietrich Wuttke: Learning Digital Test and Diagnostics via Internet. iJOE 3(1) (2007) |
| c2 | | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. European Test Symposium 2007: 131-136 |
| 2005 | ||
| c1 | | Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman: Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC 2005: 332-344 |
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