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John Dielissen
2000 – 2009
- 2008
[j3]John Dielissen, Nur Engin, Sergei Sawitzki, Kees van Berkel: Multistandard FEC Decoders for Wireless Devices. IEEE Trans. on Circuits and Systems 55-II(3): 284-288 (2008)- 2007
- [c8]John Dielissen, Andries Hekstra: Non-fractional parallelism in LDPC decoder implementations. DATE 2007: 337-342
- 2006
- [c7]John Dielissen, Andries Hekstra, Vincent Berg: Low cost LDPC decoder for DVB-S2. DATE Designers' Forum 2006: 130-135
- 2005
- [j2]Kees Goossens, John Dielissen, Andrei Radulescu: Æthereal Network on Chip: Concepts, Architectures, and Implementations. IEEE Design & Test of Computers 22(5): 414-421 (2005)
- [j1]Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees G. W. Goossens: An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 4-17 (2005)
- [c6]Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema: A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. DATE 2005: 1182-1187
- 2004
- [c5]Mauro Cocco, John Dielissen, Marc J. M. Heijligers, Andries Hekstra, Jos Huisken: A Scalable Architecture for LDPC Decodin. DATE 2004: 88-95
- [c4]Andrei Radulescu, John Dielissen, Kees G. W. Goossens, Edwin Rijpkema, Paul Wielage: An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. DATE 2004: 878-883
- 2003
- [c3]Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, E. Waterlander: Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. DATE 2003: 10350-10355
- 2002
- [c2]John Dielissen, Benito Otero Mathijssen, Jos Huisken: Breaking an application specific instruction-set processor: the first step towards embedded software testing. HLDVT 2002: 89-92
- 2001
- [c1]John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken, Albert van der Werf: Power-efficient layered turbo decoder processor. DATE 2001: 246-251
Coauthor Index
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last updated on 2012-12-02 21:03 CET by the dblp team