| 2013 | ||
|---|---|---|
| j3 | Alix Munier Kordon, Fadi Kacem, Benoît Dupont de Dinechin, Lucian Finta: Scheduling an interval ordered precedence graph with communication delays and a limited number of processors. RAIRO - Operations Research 47(1): 73-87 (2013) | |
| 2012 | ||
| j2 | Dibyendu Das, Benoît Dupont de Dinechin, Ramakrishna Upadrasta: Efficient liveness computation using merge sets and DJ-graphs. TACO 8(4): 27 (2012) | |
| c17 | Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin: K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph. ICSAMOS 2012: 152-159 | |
| 2011 | ||
| j1 | Sid Ahmed Ali Touati, Frederic Brault, Karine Deschinkel, Benoît Dupont de Dinechin: Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors. ACM Trans. Embedded Comput. Syst. 10(4): 47 (2011) | |
| c16 | Benoit Boissinot, Florian Brandner, Alain Darte, Benoît Dupont de Dinechin, Fabrice Rastello: A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs. APLAS 2011: 137-154 | |
| 2009 | ||
| c15 | Benoit Boissinot, Alain Darte, Fabrice Rastello, Benoît Dupont de Dinechin, Christophe Guillon: Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency. CGO 2009: 114-125 | |
| 2008 | ||
| c14 | Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont de Dinechin, Fabrice Rastello: Fast liveness checking for ssa-form programs. CGO 2008: 35-44 | |
| c13 | Benoît Dupont de Dinechin: Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors. Euro-Par 2008: 370-381 | |
| 2006 | ||
| c12 | Florent Blachot, Benoît Dupont de Dinechin, Guillaume Huard: SCAN: A Heuristic for Near-Optimal Software Pipelining. Euro-Par 2006: 289-298 | |
| 2005 | ||
| c11 | Jean-Michel Muller, Arnaud Tisserand, Benoît Dupont de Dinechin, Christophe Monat: Division by Constant for the ST100 DSP Microprocessor. IEEE Symposium on Computer Arithmetic 2005: 124-130 | |
| 2000 | ||
| c10 | Benoît Dupont de Dinechin, François de Ferrière, Christophe Guillon, Artour Stoutchinin: Code generator optimizations for the ST120 DSP-MCU core. CASES 2000: 93-102 | |
| 1999 | ||
| c9 | Benoît Dupont de Dinechin: Extending Modulo Scheduling with Memory Reference Merging. CC 1999: 274-287 | |
| 1997 | ||
| c8 | Robert W. Numrich, Jon L. Steidel, Brian H. Johnson, Benoît Dupont de Dinechin, Gary Elsesser, Greg Fischer, Tom MacDonald: Definition of the F-- Extension to Fortran 90. LCPC 1997: 292-306 | |
| c7 | Benoît Dupont de Dinechin: A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops. LCPC 1997: 382-393 | |
| c6 | Benoît Dupont de Dinechin: A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops. PaCT 1997: 189-200 | |
| 1996 | ||
| c5 | Benoît Dupont de Dinechin: Parametric Computation of Margins and of Minimum Cumulative Register Lifetime Dates. LCPC 1996: 231-245 | |
| 1995 | ||
| c4 | Benoît Dupont de Dinechin: Insertion Scheduling: An Alternative to List Scheduling for Modulo Schedulers. LCPC 1995: 31-45 | |
| 1994 | ||
| c3 | ||
| 1992 | ||
| c2 | ||
| 1991 | ||
| c1 | Benoît Dupont de Dinechin: A ultra fast Euclidean division algorithm for prime memory systems. SC 1991: 56-65 | |
Colors in the list of coauthors
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