Daniel Dreps

Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli, Pier Andrea Francese, Thomas Morf: A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. J. Solid-State Circuits 47(4): 897-910 (2012)

Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban: POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. J. Solid-State Circuits 46(1): 145-161 (2011)

Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin Schmatz: A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. J. Solid-State Circuits 45(12): 2850-2860 (2010)

Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin Schmatz: A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. ISSCC 2010: 160-161