Daniel M. Dreps

Rohan Mandrekar, Yaping Zhou, Sungjun Chun, Anand Haridass, Jinwoo Choi, Nanju Na, Daniel M. Dreps, Roger D. Weekly, Paul Harvey: Channel Optimization for the Design of High Speed I/O links. VLSI Design 2010: 87-92

Thomas-Michael Winkel, Hubert Harrer, Dierk Kaller, Jochen Supper, Daniel M. Dreps, Kenneth L. Christian, D. Cosmadelis, Tingdong Zhou, Thomas Strach, J. Ludwig, David L. Edwards: Packaging design challenges of the IBM System z10 Enterprise Class server. IBM Journal of Research and Development 53(1): 10 (2009)

Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng: Design methodology of high performance on-chip global interconnect using terminated transmission-line. ISQED 2009: 451-458

Kyu-hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman: A 5.4mW 0.0035mm² 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. ISSCC 2009: 98-99

Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng: Low power passive equalizer optimization using tritonic step response. DAC 2008: 570-573

Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng: Low Power Passive Equalizer Design for Computer Memory Links. Hot Interconnects 2008: 51-56

Hubert Harrer, Daniel M. Dreps, Thomas-Michael Winkel, Wolfgang Scholz, Bao G. Truong, Andreas Huber, Tingdong Zhou, Kenneth L. Christian, Gary F. Goth: High-speed interconnect and packaging design of the IBM System z9 processor cage. IBM Journal of Research and Development 51(1/2): 37-52 (2007)