DBLP: Gerhard W. Dueck

	2012
j14		Majid Mohammadi, Aliakbar Niknafs, Mohammad Eshghi, Gerhard W. Dueck: Design and Optimization of Single and Multiple-Loop Reversible and Quantum Feedback Circuits. Journal of Circuits, Systems, and Computers 21(3) (2012)
j13		Hadi Hosseini, Gerhard W. Dueck: Toffoli Gate Implementation Using The Billiard Ball Model. Multiple-Valued Logic and Soft Computing 19(1-3): 133-147 (2012)
c31		Md. Mazder Rahman, Gerhard W. Dueck: An algorithm to find quantum templates. IEEE Congress on Evolutionary Computation 2012: 1-7
c30		Md. Mazder Rahman, Gerhard W. Dueck: Optimal Quantum Circuits of Three Qubits. ISMVL 2012: 161-166
c29		Md. Mazder Rahman, Gerhard W. Dueck: Properties of Quantum Templates. RC 2012: 125-137
	2011
j12		Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging reversible circuits. Integration 44(1): 51-61 (2011)
c28		Md. Mazder Rahman, Anindita Banerjee, Gerhard W. Dueck, Anirban Pathak: Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit. ISMVL 2011: 86-92
c27		Md. Mazder Rahman, Gerhard W. Dueck, Anindita Banerjee: Optimization of Reversible Circuits Using Reconfigured Templates. RC 2011: 43-53
	2010
c26		Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Synthesizing multiplier in reversible logic. DDECS 2010: 335-340
c25		Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Window optimization of reversible and quantum circuits. DDECS 2010: 341-345
c24		Hadi Hosseini, Gerhard W. Dueck: Toffoli Gate Implementation Using the Billiard Ball Model. ISMVL 2010: 173-178
c23		Yasaman Sanaee, Gerhard W. Dueck: ESOP-Based Toffoli Network Generation with Transformations. ISMVL 2010: 276-281
	2009
j11		Gerhard W. Dueck: Editorial. Multiple-Valued Logic and Soft Computing 15(4): 265 (2009)
j10		Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits. Multiple-Valued Logic and Soft Computing 15(4): 283-300 (2009)
j9		Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 703-715 (2009)
c22		Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging of Toffoli networks. DATE 2009: 1284-1289
c21		D. Michael Miller, Robert Wille, Gerhard W. Dueck: Synthesizing Reversible Circuits for Irreversible Functions. DSD 2009: 749-756
c20		Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler: Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194
	2008
j8		Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne: Quantum Circuit Simplification and Level Compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 436-444 (2008)
c19		Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große: Quantified Synthesis of Reversible Logic. DATE 2008: 1015-1020
c18		Nathan O. Scott, Gerhard W. Dueck: Pairwise decomposition of toffoli gates in a quantum circuit. ACM Great Lakes Symposium on VLSI 2008: 231-236
c17		Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219
c16		Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler: RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225
	2007
j7		Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. 12(4) (2007)
c15		Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler: Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101
	2005
j6		Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Toffoli network synthesis with templates. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 807-817 (2005)
j5		Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. VLSI Syst. 13(6): 765-769 (2005)
c14		Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck: Quantum Circuit Simplification Using Templates. DATE 2005: 1208-1213
	2004
j4		Dmitri Maslov, Gerhard W. Dueck: Reversible cascades with minimal garbage. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1497-1509 (2004)
c13		D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov: A Synthesis Method for MVL Reversible Logi. ISMVL 2004: 74-80
	2003
c12		D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis. DAC 2003: 318-323
c11		Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD 2003: 256-261
c10		D. Michael Miller, Gerhard W. Dueck: On the Size of Multiple-Valued Decision Diagrams. ISMVL 2003: 235-240
c9		Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Simplification of Toffoli Networks via Templates. SBCCI 2003: 53-
	2001
j3		Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko: On the number of generators for transeunt triangles. Discrete Applied Mathematics 108(3): 309-316 (2001)
j2		Ping Wang, Gerhard W. Dueck, S. MacMillan: Using simulated annealing to construct extremal graphs. Discrete Mathematics 235(1-3): 125-135 (2001)
	2000
j1		Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich: Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1386-1388 (2000)
c8		Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko: Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ISMVL 2000: 141-146
	1999
c7		Gerhard W. Dueck, Mou Hu, Blair Fraser: A Super Switch Algebra for Quantum Device Based Systems. ISMVL 1999: 118-124
	1998
c6		Blair Fraser, Gerhard W. Dueck: Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. ISMVL 1998: 239-244
	1994
c5		Gerhard W. Dueck, Jon T. Butler: Multiple-Valued Logic Operations with Universal Literals. ISMVL 1994: 73-79
	1992
c4		Gerhard W. Dueck: Direct Cover MVL Minimization with Cost-Tables. ISMVL 1992: 58-65
c3		Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler: Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL 1992: 66-74
	1991
c2		Gerhard W. Dueck, G. H. John van Rees: On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. ISMVL 1991: 280-286
	1990
c1		Gerhard W. Dueck, D. Michael Miller: RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL 1990: 136-143

2012

j14

Majid Mohammadi, Aliakbar Niknafs, Mohammad Eshghi, Gerhard W. Dueck: Design and Optimization of Single and Multiple-Loop Reversible and Quantum Feedback Circuits. Journal of Circuits, Systems, and Computers 21(3) (2012)

j13

Hadi Hosseini, Gerhard W. Dueck: Toffoli Gate Implementation Using The Billiard Ball Model. Multiple-Valued Logic and Soft Computing 19(1-3): 133-147 (2012)

c31

Md. Mazder Rahman, Gerhard W. Dueck: An algorithm to find quantum templates. IEEE Congress on Evolutionary Computation 2012: 1-7

c30

Md. Mazder Rahman, Gerhard W. Dueck: Optimal Quantum Circuits of Three Qubits. ISMVL 2012: 161-166

c29

Md. Mazder Rahman, Gerhard W. Dueck: Properties of Quantum Templates. RC 2012: 125-137

2011

j12

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging reversible circuits. Integration 44(1): 51-61 (2011)

c28

Md. Mazder Rahman, Anindita Banerjee, Gerhard W. Dueck, Anirban Pathak: Two-Qubit Quantum Gates to Reduce the Quantum Cost of Reversible Circuit. ISMVL 2011: 86-92

c27

Md. Mazder Rahman, Gerhard W. Dueck, Anindita Banerjee: Optimization of Reversible Circuits Using Reconfigured Templates. RC 2011: 43-53

2010

c26

Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Synthesizing multiplier in reversible logic. DDECS 2010: 335-340

c25

Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Window optimization of reversible and quantum circuits. DDECS 2010: 341-345

c24

Hadi Hosseini, Gerhard W. Dueck: Toffoli Gate Implementation Using the Billiard Ball Model. ISMVL 2010: 173-178

c23

Yasaman Sanaee, Gerhard W. Dueck: ESOP-Based Toffoli Network Generation with Transformations. ISMVL 2010: 276-281

2009

j11

Gerhard W. Dueck: Editorial. Multiple-Valued Logic and Soft Computing 15(4): 265 (2009)

j10

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits. Multiple-Valued Logic and Soft Computing 15(4): 283-300 (2009)

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 703-715 (2009)

c22

Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging of Toffoli networks. DATE 2009: 1284-1289

c21

D. Michael Miller, Robert Wille, Gerhard W. Dueck: Synthesizing Reversible Circuits for Irreversible Functions. DSD 2009: 749-756

c20

Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler: Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194

2008

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne: Quantum Circuit Simplification and Level Compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 436-444 (2008)

c19

Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große: Quantified Synthesis of Reversible Logic. DATE 2008: 1015-1020

c18

Nathan O. Scott, Gerhard W. Dueck: Pairwise decomposition of toffoli gates in a quantum circuit. ACM Great Lakes Symposium on VLSI 2008: 231-236

c17

Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219

c16

Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler: RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225

2007

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. 12(4) (2007)

c15

Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler: Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101

2005

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Toffoli network synthesis with templates. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 807-817 (2005)

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. VLSI Syst. 13(6): 765-769 (2005)

c14

Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck: Quantum Circuit Simplification Using Templates. DATE 2005: 1208-1213

2004

Dmitri Maslov, Gerhard W. Dueck: Reversible cascades with minimal garbage. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1497-1509 (2004)

c13

D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov: A Synthesis Method for MVL Reversible Logi. ISMVL 2004: 74-80

2003

c12

D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck: A transformation based algorithm for reversible logic synthesis. DAC 2003: 318-323

c11

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD 2003: 256-261

c10

D. Michael Miller, Gerhard W. Dueck: On the Size of Multiple-Valued Decision Diagrams. ISMVL 2003: 235-240

Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Simplification of Toffoli Networks via Templates. SBCCI 2003: 53-

2001

Jon T. Butler, Gerhard W. Dueck, Svetlana N. Yanushkevich, Vlad P. Shmerko: On the number of generators for transeunt triangles. Discrete Applied Mathematics 108(3): 309-316 (2001)

Ping Wang, Gerhard W. Dueck, S. MacMillan: Using simulated annealing to construct extremal graphs. Discrete Mathematics 235(1-3): 125-135 (2001)

2000

Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko, Svetlana N. Yanushkevich: Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1386-1388 (2000)

Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko: Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ISMVL 2000: 141-146

1999

Gerhard W. Dueck, Mou Hu, Blair Fraser: A Super Switch Algebra for Quantum Device Based Systems. ISMVL 1999: 118-124

1998

Blair Fraser, Gerhard W. Dueck: Multiple-Valued Logic Minimization using Universal Literals and Cost Tables. ISMVL 1998: 239-244

1994

Gerhard W. Dueck, Jon T. Butler: Multiple-Valued Logic Operations with Universal Literals. ISMVL 1994: 73-79

1992

Gerhard W. Dueck: Direct Cover MVL Minimization with Cost-Tables. ISMVL 1992: 58-65

Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler: Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL 1992: 66-74

1991

Gerhard W. Dueck, G. H. John van Rees: On the Maximum Number of Implicants Needed to Cover a Multiple-Valued Logic Function Using Window Literals. ISMVL 1991: 280-286

1990

Gerhard W. Dueck, D. Michael Miller: RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL 1990: 136-143

1	Anindita Banerjee	[c28] [c27]
2	Jon T. Butler	[j3] [j1] [c8] [c5] [c3]
3	Xiaobo Chen	[c15]
4	Rolf Drechsler	[j12] [c26] [c25] [j10] [j9] [c22] [c20] [c17] [c16] [c15]
5	Robert C. Earle	[c3]
6	Mohammad Eshghi	[j14]
7	Blair Fraser	[c7] [c6]
8	Stefan Frehse	[j12] [c22]
9	Daniel Große	[j12] [j10] [j9] [c22] [c20] [c19] [c17] [c16] [c15]
10	Hadi Hosseini	[j13] [c24]
11	Mou Hu	[c7]
12	Hoang M. Le	[c19]
13	S. MacMillan	[j2]
14	Dmitri Maslov	[j8] [j7] [j6] [j5] [c14] [j4] [c13] [c12] [c11] [c9]
15	D. Michael Miller	[c21] [j8] [j7] [j6] [j5] [c14] [c13] [c12] [c11] [c10] [c9] [c1]
16	Majid Mohammadi	[j14]
17	Camille Negrevergne	[j8]
18	Aliakbar Niknafs	[j14]
19	Sebastian Offermann	[c26]
20	Anirban Pathak	[c28]
21	Md. Mazder Rahman	[c31] [c30] [c29] [c28] [c27]
22	G. H. John van Rees	[c2]
23	Yasaman Sanaee	[c23]
24	Nathan O. Scott	[c18]
25	Vlad P. Shmerko	[j3] [j1] [c8]
26	Mathias Soeken	[c25]
27	Lisa Teuber	[c16]
28	Parthasarathy P. Tirumalai	[c3]
29	Ping Wang	[j2]
30	Robert Wille	[j12] [c26] [c25] [j10] [j9] [c22] [c21] [c20] [c19] [c17] [c16]
31	Svetlana N. Yanushkevich	[j3] [j1] [c8]
32	Christina Young	[c14]

Gerhard W. Dueck

Coauthor Index