Nikil Dutt
List of publications from the DBLP Bibliography Server - FAQ| 2013 | ||
|---|---|---|
| j96 | Puneet Gupta, Yuvraj Agarwal, Lara Dolecek, Nikil Dutt, Rajesh K. Gupta, Rakesh Kumar, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester: Underdesigned and Opportunistic Computing in Presence of Hardware Variability. IEEE Trans. on CAD of Integrated Circuits and Systems 32(1): 8-23 (2013) | |
| c229 | Nikil Dutt, Puneet Gupta, Alex Nicolau, Luis Angel D. Bathen, Mark Gottscho: Variability-aware memory management for nanoscale computing. ASP-DAC 2013: 125-132 | |
| c228 | Yuko Hara-Azumi, Takuya Azumi, Nikil D. Dutt: VISA synthesis: Variation-aware Instruction Set Architecture synthesis. ASP-DAC 2013: 243-248 | |
| c227 | Abbas BanaiyanMofrad, Nikil Dutt, Gustavo Girão: Modeling and analysis of fault-tolerant distributed memories for networks-on-chip. DATE 2013: 1605-1608 | |
| 2012 | ||
| j95 | Kazuyuki Tanimura, Nikil D. Dutt: HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design. Embedded Systems Letters 4(3): 57-60 (2012) | |
| j94 | Chun Jason Xue, Nikil Dutt: Guest Editorial Special Section on Memory Architectures and Organization. Embedded Systems Letters 4(4): 81 (2012) | |
| j93 | Grit Denker, Nikil Dutt, Sharad Mehrotra, Mark-Oliver Stehr, Carolyn L. Talcott, Nalini Venkatasubramanian: Resilient dependable cyber-physical systems: a middleware perspective. J. Internet Services and Applications 3(1): 41-49 (2012) | |
| j92 | Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil Dutt: Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1803-1816 (2012) | |
| j91 | Kyoungwoo Lee, Nikil Dutt, Nalini Venkatasubramanian: EAVE: Error-Aware Video Encoding Supporting Extended Energy/QoS Trade-offs for Mobile Embedded Systems. ACM Trans. Embedded Comput. Syst. 11(2): 37 (2012) | |
| j90 | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian: xTune: A formal methodology for cross-layer tuning of mobile embedded systems. ACM Trans. Embedded Comput. Syst. 11(4): 73 (2012) | |
| j89 | Robert P. Dick, Li Shang, Nikil Dutt: Introduction to special section SCPS'09. ACM Trans. Embedded Comput. Syst. 11(4): 74 (2012) | |
| j88 | Ann Gordon-Ross, Frank Vahid, Nikil Dutt: Combining code reordering and cache configuration. ACM Trans. Embedded Comput. Syst. 11(4): 88 (2012) | |
| j87 | Amin Khajeh, Minyoung Kim, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi: Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications. ACM Trans. Embedded Comput. Syst. 11(S1): 15 (2012) | |
| c226 | Luis Angel D. Bathen, Mark Gottscho, Nikil Dutt, Alex Nicolau, Puneet Gupta: ViPZonE: OS-level memory variability-driven physical address zoning for energy savings. CODES+ISSS 2012: 33-42 | |
| c225 | Abbas BanaiyanMofrad, Gustavo Girão, Nikil Dutt: A novel NoC-based design for fault-tolerance of last-level caches in CMPs. CODES+ISSS 2012: 63-72 | |
| c224 | Kazuyuki Tanimura, Nikil D. Dutt: LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks. CODES+ISSS 2012: 453-462 | |
| c223 | Yi Wang, Luis Angel D. Bathen, Nikil D. Dutt, Zili Shao: Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems. DAC 2012: 214-219 | |
| c222 | Luis Angel D. Bathen, Nikil Dutt: HaVOC: a hybrid memory-aware virtualization layer for on-chip distributed ScratchPad and non-volatile memories. DAC 2012: 447-452 | |
| c221 | Luis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta: VaMV: Variability-aware Memory Virtualization. DATE 2012: 284-287 | |
| c220 | Yi Wang, Luis Angel D. Bathen, Zili Shao, Nikil D. Dutt: 3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory. DATE 2012: 1307-1312 | |
| c219 | Liviu Codrut Stancu, Luis Angel D. Bathen, Nikil Dutt, Alex Nicolau: AVid: Annotation driven video decoding for hybrid memories. ESTImedia 2012: 2-11 | |
| c218 | Michael Avery, Jeffrey L. Krichmar, Nikil Dutt: Spiking neuron model of basal forebrain enhancement of visual attention. IJCNN 2012: 1-8 | |
| c217 | ||
| c216 | Santanu Sarma, Nikil Dutt, Nalini Venkatasubramanian: Cross-layer virtual observers for embedded multiprocessor system-on-chip (MPSoC). ARM 2012: 4 | |
| c215 | ||
| c214 | Luis Angel D. Bathen, Nikil D. Dutt: Software Controlled Memories for Scalable Many-Core Architectures. RTCSA 2012: 1-10 | |
| c213 | Nikil Dutt, Mani B. Srivastava, Rajesh Gupta, Subhasish Mitra: Tutorial T6: Variability-resistant Software and Hardware for Nano-Scale Computing. VLSI Design 2012: 22-24 | |
| 2011 | ||
| j86 | Ganghee Lee, Kiyoung Choi, Nikil D. Dutt: Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 30(5): 637-650 (2011) | |
| j85 | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt: A Multi-Granularity Power Modeling Methodology for Embedded Processors. IEEE Trans. VLSI Syst. 19(4): 668-681 (2011) | |
| c212 | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian: A Formal Methodology for Compositional Cross-Layer Optimization. Formal Modeling: Actors, Open Systems, Biological Systems 2011: 207-222 | |
| c211 | Abbas BanaiyanMofrad, Houman Homayoun, Nikil Dutt: FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation. CASES 2011: 95-104 | |
| c210 | Luis Angel D. Bathen, Nikil D. Dutt, Dongyoun Shin, Sung-Soo Lim: SPMVisor: dynamic scratchpad memory virtualization for secure, low power, and high performance distributed on-chip memories. CODES+ISSS 2011: 79-88 | |
| c209 | Luis Angel D. Bathen, Nikil D. Dutt: E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories. DATE 2011: 1141-1146 | |
| c208 | Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil Dutt: Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. DATE 2011: 1513-1516 | |
| c207 | Luis Angel D. Bathen, Nikil D. Dutt: TrustGeM: Dynamic trusted environment generation for chip-multiprocessors. HOST 2011: 47-50 | |
| c206 | Jeffrey L. Krichmar, Nikil Dutt, Jayram Moorkanikara Nageswaran, Micah Richert: Neuromorphic modeling abstractions and simulation of large-scale cortical networks. ICCAD 2011: 334-338 | |
| e2 | Leon Stok, Nikil D. Dutt, Soha Hassoun (Eds.): Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011. ACM 2011, isbn 978-1-4503-0636-2 | |
| 2010 | ||
| j84 | Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian: Partitioning techniques for partially protected caches in resource-constrained embedded systems. ACM Trans. Design Autom. Electr. Syst. 15(4) (2010) | |
| j83 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt: Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. TRETS 3(3): 18 (2010) | |
| j82 | Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt: CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis. IEEE Trans. VLSI Syst. 18(2): 209-221 (2010) | |
| j81 | Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt: Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications. IEEE Trans. VLSI Syst. 18(9): 1376-1380 (2010) | |
| c205 | Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt: Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. ARC 2010: 231-243 | |
| c204 | Luis Angel D. Bathen, Nikil D. Dutt: PoliMakE: a policy making engine for secure embedded software execution on chip-multiprocessors. WESS 2010: 2 | |
| c203 | Arup Chakraborty, Houman Homayoun, Amin Khajeh, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi: E < MC2: less energy through multi-copy cache. CASES 2010: 237-246 | |
| c202 | Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt: Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. Conf. Computing Frontiers 2010: 297-308 | |
| c201 | Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt: RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. HiPEAC 2010: 216-231 | |
| c200 | Kazuyuki Tanimura, Nikil Dutt: ExCCel: Exploration of Complementary Cells for Efficient DPA Attack Resistivity. HOST 2010: 52-55 | |
| c199 | Jayram Moorkanikara Nageswaran, Micah Richert, Nikil D. Dutt, Jeffrey L. Krichmar: Towards reverse engineering the brain: Modeling abstractions and simulation frameworks. VLSI-SoC 2010: 1-6 | |
| 2009 | ||
| j80 | Nikil Dutt, Jürgen Teich: CODES+ISSS 2007 guest editors' introduction. Design Autom. for Emb. Sys. 13(1-2): 51-52 (2009) | |
| j79 | Jayram Moorkanikara Nageswaran, Andrew Felch, Ashok Chandrasekhar, Nikil Dutt, Richard Granger, Alex Nicolau, Alexander V. Veidenbaum: Brain Derived Vision Algorithm on High Performance Architectures. International Journal of Parallel Programming 37(4): 345-369 (2009) | |
| j78 | Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum: A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors. Neural Networks 22(5-6): 791-800 (2009) | |
| j77 | Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park, Yunheung Paek: Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 461-465 (2009) | |
| j76 | Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek: Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 554-567 (2009) | |
| j75 | Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt: Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. 8(3) (2009) | |
| j74 | Gabor Madl, Sudeep Pasricha, Nikil Dutt, Sherif Abdelwahed: Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs. IEEE Trans. Industrial Informatics 5(3): 241-256 (2009) | |
| j73 | Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi: System-level PVT variation-aware power exploration of on-chip communication architectures. ACM Trans. Design Autom. Electr. Syst. 14(2) (2009) | |
| j72 | Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt: Fast Configurable-Cache Tuning With a Unified Second-Level Cache. IEEE Trans. VLSI Syst. 17(1): 80-91 (2009) | |
| j71 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations. IEEE Trans. VLSI Syst. 17(2): 234-247 (2009) | |
| j70 | Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian: Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications. IEEE Trans. VLSI Syst. 17(9): 1343-1347 (2009) | |
| c198 | Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi: Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. ASP-DAC 2009: 25-30 | |
| c197 | Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir: TRAM: A tool for Temperature and Reliability Aware Memory Design. DATE 2009: 340-345 | |
| c196 | Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha: Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications. ESTImedia 2009: 45-54 | |
| c195 | Jayram Moorkanikara Nageswaran, Nikil Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum: Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors. IJCNN 2009: 2145-2152 | |
| c194 | Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Yingxue Wang, Tobi Delbrück: Computing Spike-based Convolutions on GPUs. ISCAS 2009: 1917-1920 | |
| c193 | Jayram Moorkanikara Nageswaran, Nikil D. Dutt, Yingxue Wang, Tobi Delbrück: Live Demonstration: Computing Spike-based Convolutions on GPUs. ISCAS 2009: 1921 | |
| c192 | Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha: A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations. MTV 2009: 19-24 | |
| c191 | Gabor Madl, Nikil Dutt, Sherif Abdelwahed: A Conservative Approximation Method for the Verification of Preemptive Scheduling Using Timed Automata. IEEE Real-Time and Embedded Technology and Applications Symposium 2009: 255-264 | |
| c190 | Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi: Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. VLSI Design 2009: 499-504 | |
| 2008 | ||
| j69 | Jong-eun Lee, Kiyoung Choi, Nikil Dutt: Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures. IJES 3(3): 119-127 (2008) | |
| j68 | Ilya Issenin, Nikil Dutt: Using FORAY Models to Enable MPSoC Memory Optimizations. International Journal of Parallel Programming 36(1): 93-113 (2008) | |
| j67 | Gabor Madl, Nikil Dutt: Real-time analysis of resource-constrained distributed systems by simulation-guided model checking. SIGBED Review 5(1): 7 (2008) | |
| j66 | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie: Register File Power Reduction Using Bypass Sensitive Compiler. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1155-1159 (2008) | |
| j65 | Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt: Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1439-1452 (2008) | |
| j64 | Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian: Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies. ACM Trans. Embedded Comput. Syst. 7(2) (2008) | |
| j63 | Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane: Fast exploration of bus-based communication architectures at the CCATB abstraction. ACM Trans. Embedded Comput. Syst. 7(2) (2008) | |
| j62 | ||
| j61 | ||
| j60 | ||
| j59 | Prabhat Mishra, Nikil Dutt: Specification-driven directed test generation for validation of pipelined processors. ACM Trans. Design Autom. Electr. Syst. 13(3) (2008) | |
| c189 | Aviral Shrivastava, Ilya Issenin, Nikil Dutt: A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures. ASP-DAC 2008: 328-333 | |
| c188 | Sudeep Pasricha, Nikil Dutt: ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip. ASP-DAC 2008: 789-794 | |
| c187 | ||
| c186 | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt: Methodology for multi-granularity embedded processor power model generation for an ESL design flow. CODES+ISSS 2008: 255-260 | |
| c185 | Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil Dutt, Giovanni Mancini: ESL hand-off: fact or EDA fiction? DAC 2008: 310-312 | |
| c184 | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian: Constraint Refinement for Online Verifiable Cross-Layer System Adaptation. DATE 2008: 646-651 | |
| c183 | ||
| c182 | Amin Khajeh Djahromi, Minyoung Kim, Nikil Dutt, Ahmed M. Eltawil, Fadi J. Kurdahi: Cross-layer co-exploration of exploiting error resilience for video over wireless applications. ESTImedia 2008: 13-18 | |
| c181 | Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasricha: A framework for memory-aware multimedia application mapping on chip-multiprocessors. ESTImedia 2008: 89-94 | |
| c180 | Kyoungwoo Lee, Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian: Error-Exploiting Video Encoder to Extend Energy/QoS Tradeoffs for Mobile Embedded Systems. DIPES 2008: 23-34 | |
| c179 | Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt, Nalini Venkatasubramanian: Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. DIPES 2008: 213-225 | |
| c178 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. ISQED 2008: 470-475 | |
| c177 | Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil Dutt, Yunheung Paek, SunJun Ko: Compiler driven data layout optimization for regular/irregular array access patterns. LCTES 2008: 41-50 | |
| c176 | Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt, Nalini Venkatasubramanian: Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach. ACM Multimedia 2008: 319-328 | |
| c175 | Fadi J. Kurdahi, Nikil Dutt, Ahmed M. Eltawil, Sani R. Nassif: Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips. VLSI Design 2008: 14-15 | |
| c174 | Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt: Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. VLSI Design 2008: 363-370 | |
| c173 | Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi: PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. VLSI Design 2008: 421-427 | |
| 2007 | ||
| j58 | Liang Cheng, Shivajit Mohapatra, Magda El Zarki, Nikil D. Dutt, Nalini Venkatasubramanian: Quality-Based Backlight Optimization for Video Playback on Handheld Devices. Adv. in MM 2007 (2007) | |
| j57 | Chulho Shin, Peter Grun, Nizar Romdhane, Christopher K. Lennard, Gabor Madl, Sudeep Pasricha, Nikil Dutt, Mark Noll: Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications. Design Autom. for Emb. Sys. 11(2-3): 119-140 (2007) | |
| j56 | Shivajit Mohapatra, Nikil Dutt, Alexandru Nicolau, Nalini Venkatasubramanian: DYNAMO: A Cross-Layer Framework for End-to-End QoS and Energy Optimization in Mobile Handheld Devices. IEEE Journal on Selected Areas in Communications 25(4): 722-737 (2007) | |
| j55 | Sudeep Pasricha, Nikil D. Dutt: A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 408-420 (2007) | |
| j54 | Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: Introduction of Architecturally Visible Storage in Instruction Set Extensions. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 435-446 (2007) | |
| j53 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1454-1464 (2007) | |
| j52 | Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek: Automatic Design Space Exploration of Register Bypasses in Embedded Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2102-2115 (2007) | |
| j51 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Instruction set synthesis with efficient instruction encoding for configurable processors. ACM Trans. Design Autom. Electr. Syst. 12(1) (2007) | |
| j50 | ||
| j49 | Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt: DRDU: A data reuse analysis technique for efficient scratch-pad memory management. ACM Trans. Design Autom. Electr. Syst. 12(2) (2007) | |
| p1 | Aviral Shrivastava, Nikil Dutt: Compiler Aided Design of Embedded Computers. The Compiler Design Handbook, 2nd ed. 2007: 3 | |
| c172 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ASP-DAC 2007: 274-279 | |
| c171 | Doosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek: Software controlled memory layout reorganization for irregular array access patterns. CASES 2007: 179-188 | |
| c170 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera: Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. DAC 2007: 771-776 | |
| c169 | Qiang Zhu, Aviral Shrivastava, Nikil Dutt: Interactive presentation: Functional and timing validation of partially bypassed processor pipelines. DATE 2007: 1164-1169 | |
| c168 | Gabor Madl, Nikil Dutt, Sherif Abdelwahed: Performance estimation of distributed real-time embedded systems by discrete event simulations. EMSOFT 2007: 183-192 | |
| c167 | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil D. Dutt, Nalini Venkatasubramanian: A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded Systems. FMOODS 2007: 285-300 | |
| c166 | Minyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil Dutt, Nalini Venkatasubramanian: Combining Formal Verification with Observed System Execution Behavior to Tune System Parameters. FORMATS 2007: 257-273 | |
| c165 | Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt: System level power estimation methodology with H.264 decoder prediction IP case study. ICCD 2007: 601-608 | |
| c164 | Ilya Issenin, Nikil Dutt: Data Reuse Driven Memory and Network-On-Chip Co-Synthesis. IESS 2007: 299-312 | |
| c163 | ||
| c162 | Radu Cornea, Alex Nicolau, Nikil Dutt: Annotation Integration and Trade-off Analysis for Multimedia Applications. IPDPS 2007: 1-6 | |
| c161 | Jeff Furlong, Andrew Felch, Jayram Moorkanikara Nageswaran, Nikil Dutt, Alex Nicolau, Alexander V. Veidenbaum, Ashok Chandrashekar, Richard Granger: Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements. PARCO 2007: 767-776 | |
| c160 | Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha: Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. VLSI Design 2007: 8 | |
| c159 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. VLSI Design 2007: 559-564 | |
| e1 | Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich (Eds.): Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007. ACM 2007, isbn 978-1-59593-824-4 | |
| i3 | Ilya Issenin, Nikil Dutt: FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. CoRR abs/0710.4640 (2007) | |
| i2 | Mehrdad Reshadi, Nikil Dutt: Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation. CoRR abs/0710.4643 (2007) | |
| i1 | Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. CoRR abs/0710.4820 (2007) | |
| 2006 | ||
| j48 | Minyoung Kim, Hyunok Oh, Nikil Dutt, Alex Nicolau, Nalini Venkatasubramanian: PBPAIR: an energy-efficient error-resilient encoding using probability based power aware intra refresh. Mobile Computing and Communications Review 10(3): 58-69 (2006) | |
| j47 | Mehrdad Reshadi, Bita Gorjiara, Nikil D. Dutt: Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2904-2918 (2006) | |
| j46 | Mehrdad Reshadi, Nikil Dutt, Prabhat Mishra: A retargetable framework for instruction-set architecture simulation. ACM Trans. Embedded Comput. Syst. 5(2): 431-452 (2006) | |
| j45 | ||
| j44 | Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). ACM Trans. Design Autom. Electr. Syst. 11(1): 123-146 (2006) | |
| j43 | Prabhat Mishra, Aviral Shrivastava, Nikil Dutt: Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. ACM Trans. Design Autom. Electr. Syst. 11(3): 626-658 (2006) | |
| j42 | Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane: FABSYN: floorplan-aware bus architecture synthesis. IEEE Trans. VLSI Syst. 14(3): 241-253 (2006) | |
| j41 | Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil D. Dutt, Rajesh K. Gupta: Energy efficient watermarking on mobile devices using proxy-based partitioning. IEEE Trans. VLSI Syst. 14(6): 625-636 (2006) | |
| j40 | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. VLSI Syst. 14(7): 754-762 (2006) | |
| j39 | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Retargetable pipeline hazard detection for partially bypassed processors. IEEE Trans. VLSI Syst. 14(8): 791-801 (2006) | |
| j38 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. IEEE Trans. VLSI Syst. 14(11): 1189-1202 (2006) | |
| c158 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: Constraint-driven bus matrix synthesis for MPSoC. ASP-DAC 2006: 30-35 | |
| c157 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt: PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. ASP-DAC 2006: 491-496 | |
| c156 | Hyunok Oh, Nikil Dutt, Soonhoi Ha: Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs. ASP-DAC 2006: 497-502 | |
| c155 | Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Nalini Venkatasubramanian: Mitigating soft error failures for multimedia applications by selective data protection. CASES 2006: 411-420 | |
| c154 | Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian: Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies. CODES+ISSS 2006: 16-21 | |
| c153 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: Floorplan driven leakage power aware IP-based SoC design space exploration. CODES+ISSS 2006: 118-123 | |
| c152 | Ilya Issenin, Nikil Dutt: Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications. CODES+ISSS 2006: 294-299 | |
| c151 | Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt: System-level power-performance trade-offs in bus matrix communication architecture synthesis. CODES+ISSS 2006: 300-305 | |
| c150 | Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil Dutt: Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies. DAC 2006: 49-52 | |
| c149 | Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi: Automatic identification of application-specific functional units with architecturally visible storage. DATE 2006: 212-217 | |
| c148 | Radu Cornea, Alexandru Nicolau, Nikil D. Dutt: Software annotations for power optimization on mobile devices. DATE 2006: 684-689 | |
| c147 | Sudeep Pasricha, Nikil D. Dutt: COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC. DATE 2006: 700-705 | |
| c146 | Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil Dutt, Yunheung Paek: Automatic generation of operation tables for fast exploration of bypasses in embedded processors. DATE 2006: 1197-1202 | |
| c145 | Gabor Madl, Sudeep Pasricha, Luis Angel D. Bathen, Nikil Dutt, Qiang Zhu: Formal performance evaluation of AMBA-based system-on-chip designs. EMSOFT 2006: 311-320 | |
| c144 | Radu Cornea, Alex Nicolau, Nikil Dutt: Annotation Based Multimedia Streaming Over Wireless Networks. ESTImedia 2006: 47-52 | |
| c143 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil Dutt: Minimizing peak power for application chains on architectures with partial dynamic reconfiguration. FPT 2006: 273-276 | |
| c142 | Radu Cornea, Alex Nicolau, Nikil Dutt: Video Stream Annotations for Energy Trade-offs in Multimedia Applications. ISPDC 2006: 17-23 | |
| c141 | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie: Bypass aware instruction scheduling for register file power reduction. LCTES 2006: 173-181 | |
| c140 | Gabor Madl, Nikil Dutt: Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems. SAMOS 2006: 59-68 | |
| c139 | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi: Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design 2006: 651-656 | |
| 2005 | ||
| b2 | Prabhat Mishra, Nikil D. Dutt: Functional verification of programmable embedded architectures - a top-down approach. Springer 2005, isbn 978-0-387-26143-0, pp. I-XVIII, 1-180 | |
| j37 | Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A methodology for validation of microprocessors using symbolic simulation. IJES 1(1/2): 14-22 (2005) | |
| j36 | Partha Biswas, Nikil D. Dutt: Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. IEEE Trans. Computers 54(10): 1216-1226 (2005) | |
| j35 | ||
| c138 | Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane: Automated throughput-driven synthesis of bus-based communication architectures. ASP-DAC 2005: 495-498 | |
| c137 | Jaewon Seo, Nikil D. Dutt: A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors. ASP-DAC 2005: 836-841 | |
| c136 | Aviral Shrivastava, Ilya Issenin, Nikil Dutt: Compilation techniques for energy reduction in horizontally partitioned cache architectures. CASES 2005: 90-96 | |
| c135 | Hyunok Oh, Nikil D. Dutt, Soonhoi Ha: Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs. CASES 2005: 157-165 | |
| c134 | Hyunok Oh, Nikil D. Dutt, Soonhoi Ha: Shift buffering technique for automatic code synthesis from synchronous dataflow graphs. CODES+ISSS 2005: 51-56 | |
| c133 | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Aggregating processor free time for energy reduction. CODES+ISSS 2005: 154-159 | |
| c132 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. DAC 2005: 335-340 | |
| c131 | Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane: Floorplan-aware automated synthesis of bus-based communication architectures. DAC 2005: 565-570 | |
| c130 | Prabhat Mishra, Nikil D. Dutt: Functional Coverage Driven Test Generation for Validation of Pipelined Processors. DATE 2005: 678-683 | |
| c129 | Mehrdad Reshadi, Nikil D. Dutt: Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation. DATE 2005: 786-791 | |
| c128 | Ilya Issenin, Nikil D. Dutt: FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations. DATE 2005: 808-813 | |
| c127 | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE 2005: 1246-1251 | |
| c126 | Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie: PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. DATE 2005: 1264-1269 | |
| c125 | Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta: Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices. ESTImedia 2005: 33-38 | |
| c124 | Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. FCCM 2005: 273-274 | |
| c123 | Ann Gordon-Ross, Frank Vahid, Nikil Dutt: A first look at the interplay of code reordering and configurable caches. ACM Great Lakes Symposium on VLSI 2005: 416-421 | |
| c122 | Jaewon Seo, Taewhan Kim, Nikil D. Dutt: Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. ICCAD 2005: 450-455 | |
| c121 | Minyoung Kim, Hyunok Oh, Nikil D. Dutt, Alexandru Nicolau, Nalini Venkatasubramanian: Probability Based Power Aware Error Resilient Coding. ICDCS Workshops 2005: 307-313 | |
| c120 | Kyoungwoo Lee, Nikil Dutt, Nalini Venkatasubramanian: An Experimental Study on Energy Consumption of Video Encryption for Mobile Handheld Devices. ICME 2005: 1424-1427 | |
| c119 | Liang Cheng, Stefano Bossi, Shivajit Mohapatra, Magda El Zarki, Nalini Venkatasubramanian, Nikil D. Dutt: Quality Adapted Backlight Scaling (QABS) for Video Streaming to Mobile Handheld Devices. ICN (1) 2005: 662-671 | |
| c118 | Shivajit Mohapatra, Radu Cornea, Hyunok Oh, Kyoungwoo Lee, Minyoung Kim, Nikil D. Dutt, Rajesh Gupta, Alexandru Nicolau, Sandeep K. Shukla, Nalini Venkatasubramanian: A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems. IPDPS 2005 | |
| c117 | Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt: Fast configurable-cache tuning with a unified second-level cache. ISLPED 2005: 323-326 | |
| c116 | Brian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt: An Introduction to the Plasma Language. MTV 2005: 12-22 | |
| 2004 | ||
| j34 | Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A Top-Down Methodology for Microprocessor Validation. IEEE Design & Test of Computers 21(2): 122-131 (2004) | |
| j33 | Sudeep Pasricha, Manev Luthra, Shivajit Mohapatra, Nikil D. Dutt, Nalini Venkatasubramanian: Dynamic Backlight Adaptation for Low-Power Handheld Devices. IEEE Design & Test of Computers 21(5): 398-405 (2004) | |
| j32 | Hiroyuki Tomiyama, Nikil Dutt: ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts. IEICE Transactions 87-D(6): 1582-1587 (2004) | |
| j31 | Sumit Gupta, Nicolae Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Using global code motions to improve the quality of results for high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 302-312 (2004) | |
| j30 | Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: IDAP: a tool for high-level power estimation of custom array structures. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1361-1369 (2004) | |
| j29 | Prabhat Mishra, Nikil Dutt: Modeling and validation of pipeline specifications. ACM Trans. Embedded Comput. Syst. 3(1): 114-139 (2004) | |
| j28 | Prabhat Mishra, Mahesh Mamidipaka, Nikil Dutt: Processor-memory coexploration using an architecture description language. ACM Trans. Embedded Comput. Syst. 3(1): 140-162 (2004) | |
| j27 | Sumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau: Coordinated parallelizing compiler optimizations and high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 9(4): 441-470 (2004) | |
| c115 | Aviral Shrivastava, Nikil D. Dutt: Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA). ASP-DAC 2004: 475-477 | |
| c114 | Sudarshan Banerjee, Nikil D. Dutt: Efficient search space exploration for HW-SW partitioning. CODES+ISSS 2004: 122-127 | |
| c113 | Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: Analytical models for leakage power estimation of memory array structures. CODES+ISSS 2004: 146-151 | |
| c112 | Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Operation tables for scheduling in the presence of incomplete bypassing. CODES+ISSS 2004: 194-199 | |
| c111 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: Fast exploration of bus-based on-chip communication architectures. CODES+ISSS 2004: 242-247 | |
| c110 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: Extending the transaction level modeling approach for fast communication architecture exploration. DAC 2004: 113-118 | |
| c109 | Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil Dutt, Rajesh Gupta: Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices. DAC 2004: 556-561 | |
| c108 | Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt: Introduction of local memory elements in instruction set extensions. DAC 2004: 729-734 | |
| c107 | Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru Nicolau: Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow. DATE 2004: 114-121 | |
| c106 | Prabhat Mishra, Nikil Dutt: Graph-Based Functional Test Program Generation for Pipelined Processors. DATE 2004: 182-187 | |
| c105 | Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt: Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies. DATE 2004: 202-207 | |
| c104 | Ann Gordon-Ross, Frank Vahid, Nikil Dutt: Automatic Tuning of Two-Level Caches to Embedded Applications. DATE 2004: 208-213 | |
| c103 | Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alexandru Nicolau, Rajesh Gupta: Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures. DATE 2004: 474-479 | |
| c102 | Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta, Shivajit Mohapatra, Cristiano Pereira, Nalini Venkatasubramanian, Ralph von Vignau: Energy-Aware System Design for Wireless Multimedia. DATE 2004: 1124-1131 | |
| c101 | ||
| c100 | Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta: Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures. FPL 2004: 891-899 | |
| c99 | Sudarshan Banerjee, Nikil D. Dutt: FIFO power optimization for on-chip networks. ACM Great Lakes Symposium on VLSI 2004: 187-191 | |
| c98 | Prabhat Mishra, Nikil D. Dutt, Yaron Kashai: Functional Verification of Pipelined Processors: A Case Study. MTV 2004: 79-84 | |
| c97 | Prabhat Mishra, Arun Kejariwal, Nikil Dutt: Synthesis-driven Exploration of Pipelined Embedded Processors. VLSI Design 2004: 921-926 | |
| 2003 | ||
| b1 | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Memory architecture exploration for programmable embedded systems. Kluwer 2003, isbn 978-1-4020-7324-3, pp. I-XVI, 1-128 | |
| j26 | Nikil D. Dutt, Kiyoung Choi: Configurable Processors for Embedded Computing. IEEE Computer 36(1): 120-123 (2003) | |
| j25 | Prabhat Mishra, Nikil Dutt, Hiroyuki Tomiyama: Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications. Design Autom. for Emb. Sys. 8(2-3): 249-265 (2003) | |
| j24 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Compilation Approach for Coarse-Grained Reconfigurable Architectures. IEEE Design & Test of Computers 20(1): 26-33 (2003) | |
| j23 | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Access pattern-based memory and connectivity architecture exploration. ACM Trans. Embedded Comput. Syst. 2(1): 33-73 (2003) | |
| j22 | Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions. IEEE Trans. VLSI Syst. 11(4): 731-737 (2003) | |
| j21 | Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt: Adaptive low-power address encoding techniques using self-organizing lists. IEEE Trans. VLSI Syst. 11(5): 827-834 (2003) | |
| c96 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. ASAP 2003: 172-182 | |
| c95 | Partha Biswas, Nikil D. Dutt: Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. CASES 2003: 104-112 | |
| c94 | Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt: An efficient retargetable framework for instruction-set simulation. CODES+ISSS 2003: 13-18 | |
| c93 | Nikil D. Dutt, Janos Sztipanovits, Masaki Hirata: Driving agenda for systems research. CODES+ISSS 2003: 82 | |
| c92 | Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt: Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. DAC 2003: 758-763 | |
| c91 | Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. DATE 2003: 10270-10275 | |
| c90 | Mahesh Mamidipaka, Nikil D. Dutt: On-chip Stack Based Memory Organization for Low Power Embedded Architectures. DATE 2003: 11082-11089 | |
| c89 | Sudeep Pasricha, Shivajit Mohapatra, Manev Luthra, Nikil D. Dutt, Nalini Venkatasubramanian: Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices. ESTImedia 2003: 11-17 | |
| c88 | Hiroyuki Tomiyama, Hiroaki Takada, Nikil D. Dutt: Data Organization Exploration for Low-Energy Address Buses. ESTImedia 2003: 128-133 | |
| c87 | Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: IDAP: A Tool for High Level Power Estimation of Custom Array Structures. ICCAD 2003: 113-119 | |
| c86 | Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Interface Synthesis using Memory Mapping for an FPGA Platform. ICCD 2003: 140-145 | |
| c85 | Mehrdad Reshadi, Nikil D. Dutt: Reducing Compilation Time Overhead in Compiled Simulators. ICCD 2003: 151- | |
| c84 | Radu Cornea, Nikil D. Dutt, Rajesh K. Gupta, Ingolf Krüger, Alexandru Nicolau, Douglas C. Schmidt, Sandeep K. Shukla: FORGE: A Framework for Optimization of Distributed Embedded Systems Software. IPDPS 2003: 208 | |
| c83 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Energy-efficient instruction set synthesis for application-specific processors. ISLPED 2003: 330-333 | |
| c82 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: An algorithm for mapping loops onto coarse-grained reconfigurable architectures. LCTES 2003: 183-188 | |
| c81 | Shivajit Mohapatra, Radu Cornea, Nikil D. Dutt, Alexandru Nicolau, Nalini Venkatasubramanian: Integrated power management for video streaming to mobile handheld devices. ACM Multimedia 2003: 582-591 | |
| c80 | Prabhat Mishra, Nikil D. Dutt: A Methodology for Validation of Microprocessors using Equivalence Checking. MTV 2003: 83-88 | |
| c79 | Prabhat Mishra, Arun Kejariwal, Nikil Dutt: Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models. IEEE International Workshop on Rapid System Prototyping 2003: 226-232 | |
| c78 | Marcio Buss, Tony Givargis, Nikil D. Dutt: Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores. RTSS 2003: 275-281 | |
| c77 | Mahesh Mamidipaka, Nikil D. Dutt, Kamal S. Khouri: A Methodology for Accurate Modeling of Energy Dissipation in Array Structures. VLSI Design 2003: 320- | |
| c76 | Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations. VLSI Design 2003: 461-466 | |
| 2002 | ||
| c75 | Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau, Timothy Kam, Michael Kishinevsky, Shai Rotem: Coordinated transformations for high-level synthesis of high performance microprocessor blocks. DAC 2002: 898-903 | |
| c74 | Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama: Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. DATE 2002: 36-43 | |
| c73 | Ana Azevedo, Ilya Issenin, Radu Cornea, Rajesh Gupta, Nikil D. Dutt, Alexander V. Veidenbaum, Alexandru Nicolau: Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints. DATE 2002: 168-175 | |
| c72 | Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau: An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. DATE 2002: 402-408 | |
| c71 | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Memory System Connectivity Exploration. DATE 2002: 894-901 | |
| c70 | Preeti Ranjan Panda, Nikil D. Dutt: Memory Architectures for Embedded Systems-On-Chip. HiPC 2002: 647-662 | |
| c69 | Prabhat Mishra, Nikil Dutt: Automatic functional test program generation for pipelined processors using model checking. HLDVT 2002: 99-103 | |
| c68 | Jong-eun Lee, Kiyoung Choi, Nikil Dutt: Efficient instruction encoding for automatic instruction set design of configurable ASIPs. ICCAD 2002: 649-654 | |
| c67 | Prabhat Mishra, Nikil D. Dutt: Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions. DIPES 2002: 81-90 | |
| c66 | Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi: A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . ISSS 2002: 120-125 | |
| c65 | Nikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka: Efficient Power Reduction Techniques for Time Multiplexed Address Buses. ISSS 2002: 207-212 | |
| c64 | Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta: Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. ISSS 2002: 261-266 | |
| c63 | Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. VLSI Design 2002: 458- | |
| 2001 | ||
| j20 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef: Data Memory Organization and Optimizations in Application-Specific Systems. IEEE Design & Test of Computers 18(3): 56-68 (2001) | |
| j19 | Francky Catthoor, Koen Danckaert, Sven Wuytack, Nikil D. Dutt: Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors. IEEE Design & Test of Computers 18(3): 70-82 (2001) | |
| j18 | Asheesh Khare, Ashok Halambi, Nicolae Savoiu, Peter Grun, Nikil Dutt, Alex Nicolau: V-SAT: A visual specification and analysis tool for system-on-chip exploration. Journal of Systems Architecture 47(3-4): 263-275 (2001) | |
| j17 | Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg: Data and memory optimization techniques for embedded systems. ACM Trans. Design Autom. Electr. Syst. 6(2): 149-206 (2001) | |
| c62 | Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi: New directions in compiler technology for embedded systems (embedded tutorial). ASP-DAC 2001: 409-414 | |
| c61 | Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Speculation Techniques for High Level Synthesis of Control Intensive Designs. DAC 2001: 269-272 | |
| c60 | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Access pattern based local memory customization for low power embedded systems. DATE 2001: 778-784 | |
| c59 | Prabhat Mishra, Nikil Dutt, Alex Nicolau: Automatic validation of pipeline specifications. HLDVT 2001: 9-13 | |
| c58 | Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil Dutt: Low power address encoding using self-organizing lists. ISLPED 2001: 188-193 | |
| c57 | ||
| c56 | Sumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau: Conditional speculation and its effects on performance and area for high-level snthesis. ISSS 2001: 171-176 | |
| c55 | Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau: Functional abstraction driven design space exploration of heterogeneous programmable architectures. ISSS 2001: 256-261 | |
| c54 | Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. VLSI Design 2001: 70-75 | |
| c53 | Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt: Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. VLSI Design 2001: 97-102 | |
| 2000 | ||
| j16 | Pradip K. Jha, Nikil D. Dutt: High-level library mapping for memories. ACM Trans. Design Autom. Electr. Syst. 5(3): 566-603 (2000) | |
| j15 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Trans. Design Autom. Electr. Syst. 5(3): 682-704 (2000) | |
| j14 | Allen C.-H. Wu, Nikil D. Dutt: Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). IEEE Trans. VLSI Syst. 8(5): 469-471 (2000) | |
| c52 | Hiroyuki Tomiyama, Nikil D. Dutt: Program path analysis to bound cache-related preemption delay in preemptive real-time systems. CODES 2000: 67-71 | |
| c51 | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Memory aware compilation through accurate timing extraction. DAC 2000: 316-321 | |
| c50 | Francky Catthoor, Nikil D. Dutt, Christoforos E. Kozyrakis: How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? DATE 2000: 426-433 | |
| c49 | Ashok Halambi, Radu Cornea, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Architecture Exploration of Parameterizable EPIC SOC Architectures. DATE 2000: 748 | |
| c48 | Hiroyuki Tomiyama, Taisei Yoshino, Nikil Dutt: Verification of in-order execution in pipelined processors. HLDVT 2000: 40-44 | |
| c47 | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: MIST: An Algorithm for Memory Miss Traffic Management. ICCAD 2000: 431-437 | |
| c46 | Lode Nachtergaele, Vivek Tiwari, Nikil D. Dutt: System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications. ICCAD 2000: 569-573 | |
| c45 | Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: Customizing Software Toolkits for Embedded Systems-On-Chip. DIPES 2000: 87-98 | |
| c44 | Peter Grun, Nikil D. Dutt, Alexandru Nicolau: Aggressive Memory-Aware Compilation. Intelligent Memory Systems 2000: 147-151 | |
| 1999 | ||
| j13 | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau: Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. IEEE Trans. Computers 48(2): 142-149 (1999) | |
| j12 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Local memory exploration and optimization in embedded systems. IEEE Trans. on CAD of Integrated Circuits and Systems 18(1): 3-13 (1999) | |
| j11 | Preeti Ranjan Panda, Nikil D. Dutt: Low-power memory mapping through reducing address bus activity. IEEE Trans. VLSI Syst. 7(3): 309-320 (1999) | |
| c43 | Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil D. Dutt, Alexandru Nicolau: EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. DATE 1999: 485-490 | |
| c42 | Asheesh Khare, Nicolae Savoiu, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau: V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration. EUROMICRO 1999: 1196-1203 | |
| c41 | ||
| c40 | Nikil D. Dutt, Brian Kelley: On the rapid prototyping and design of a wireless communication system on a chip (abstract). ICCAD 1999: 609 | |
| c39 | Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau: RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions. ISSS 1999: 44-50 | |
| 1998 | ||
| j10 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Incorporating DRAM access modes into high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 96-109 (1998) | |
| c38 | Peter Grun, Florin Balasa, Nikil D. Dutt: Memory size estimation for multimedia applications. CODES 1998: 145-149 | |
| c37 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Data Cache Sizing for Embedded Processor Applications. DATE 1998: 925-926 | |
| c36 | Soren Hein, Vijay Nagasamy, Bernhard Rohfleisch, Christoforos E. Kozyrakis, Nikil D. Dutt, Francky Catthoor: Embedded memories in system design - from technology to systems architecture. ICCAD 1998: 1 | |
| c35 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt: Copy Elimination for Parallelizing Compilers. LCPC 1998: 275-289 | |
| 1997 | ||
| j9 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt: A unified lower bound estimation technique for high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 458-472 (1997) | |
| j8 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Memory data organization for improved cache performance in embedded processor applications. ACM Trans. Design Autom. Electr. Syst. 2(4): 384-409 (1997) | |
| c34 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Efficient utilization of scratch-pad memory in embedded processor applications. ED&TC 1997: 7-11 | |
| c33 | ||
| c32 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Exploiting off-chip memory access modes in high-level synthesis. ICCAD 1997: 333-340 | |
| c31 | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau: A Data Alignment Technique for Improving Cache Performance. ICCD 1997: 587-592 | |
| c30 | Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau: Improving cache Performance Through Tiling and Data Alignment. IRREGULAR 1997: 167-185 | |
| c29 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Architectural Exploration and Optimization of Local Memory in Embedded Systems. ISSS 1997: 90- | |
| c28 | Preeti Ranjan Panda, Nikil D. Dutt: Behavioral Array Mapping into Multiport Memories Targeting Low Power. VLSI Design 1997: 268-273 | |
| 1996 | ||
| j7 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt: Elimination of redundant memory traffic in high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1354-1364 (1996) | |
| j6 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy: Optimal register assignment to loops for embedded code generation. ACM Trans. Design Autom. Electr. Syst. 1(2): 251-279 (1996) | |
| j5 | Pradip K. Jha, Nikil D. Dutt: High-level library mapping for arithmetic components. IEEE Trans. VLSI Syst. 4(2): 157-169 (1996) | |
| c27 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt, Ken Kennedy: A Method for Register Allocation to Loops in Multiple Register File Architectures. IPPS 1996: 28-33 | |
| c26 | Preeti Ranjan Panda, Nikil D. Dutt: Low-power mapping of behavioral arrays to multiple memories. ISLPED 1996: 289-292 | |
| c25 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Memory Organization for Improved Data Cache Performance in Embedded Processors. ISSS 1996: 90-95 | |
| 1995 | ||
| j4 | Andrea Capitanio, Alexandru Nicolau, Nikil Dutt: A hypergraph-based model for port allocation on multiple-register-file VLIW architectures. International Journal of Parallel Programming 23(6): 499-513 (1995) | |
| c24 | ||
| c23 | David J. Kolson, Alexandru Nicolau, Nikil Dutt, Ken Kennedy: Optimal register assignment to loops for embedded code generation. ISSS 1995: 42-47 | |
| c22 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu: A comprehensive estimation technique for high-level synthesis. ISSS 1995: 122-127 | |
| c21 | ||
| 1994 | ||
| c20 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt: Minimization of Memory Traffic in High-Level Synthesis. DAC 1994: 149-154 | |
| c19 | Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura: Design Reuse: Fact or Fiction? (Panel). DAC 1994: 562 | |
| c18 | Steven Novack, Alexandru Nicolau, Nikil D. Dutt: A Unified code generation approach using mutation scheduling. Code Generation for Embedded Processors 1994: 203-218 | |
| c17 | David J. Kolson, Alexandru Nicolau, Nikil D. Dutt: Integrating program transformations in the memory-based synthesis of image and video algorithms. ICCAD 1994: 27-30 | |
| c16 | Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt: Comprehensive lower bound estimation from behavioral descriptions. ICCAD 1994: 182-187 | |
| c15 | Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau: Partitioning of Variables for Multiple-Register-File VLIW Architectures. ICPP (1) 1994: 298-301 | |
| c14 | Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau: Partitioning of Variables for Multiple-Register-File Architectures via Hypergraph Coloring. IFIP PACT 1994: 319-322 | |
| c13 | Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt, Fadi J. Kurdahi: An Empirical Study on the Effects of Physical Design in High-Level Synthesis. VLSI Design 1994: 11-16 | |
| c12 | David J. Kolson, Nikil D. Dutt, Alexandru Nicolau: Ultra Fine-Grain Template-Driven Synthesis. VLSI Design 1994: 25-28 | |
| c11 | Pradip K. Jha, Nikil D. Dutt: Rapid Technology Projection for High-Level Synthesis. VLSI Design 1994: 155-158 | |
| 1993 | ||
| j3 | Nikil D. Dutt: A language for designer controlled behavioral synthesis. Integration 16(1): 1-31 (1993) | |
| j2 | Pradip K. Jha, Nikil D. Dutt: Rapid estimation for parameterized components in high-level synthesis. IEEE Trans. VLSI Syst. 1(3): 296-303 (1993) | |
| c10 | Roger P. Ang, Nikil D. Dutt: A Representation for the Binding of RT-Component Functionality to HDL Behavior. CHDL 1993: 263-280 | |
| c9 | Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau, Kai-Yeung Siu: High-Level Synthesis of Scalable Architectures for IIR Filters using Multichip Modules. DAC 1993: 336-342 | |
| c8 | Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau: Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried Dependencies. VLSI Design 1993: 198-201 | |
| 1992 | ||
| c7 | Roger P. Ang, Nikil D. Dutt: Equivalent design representations and transformations for interactive scheduling. ICCAD 1992: 332-335 | |
| c6 | Daniel Gajski, Nikil D. Dutt: Benchmarking and the Art of Syntesis Tool Comparison. Synthesis for Control Dominated Circuits 1992: 439-453 | |
| c5 | Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau: Partitioned register files for VLIWs: a preliminary analysis of tradeoffs. MICRO 1992: 292-300 | |
| 1991 | ||
| c4 | Nikil D. Dutt, James R. Kipps: Bridging High-Level Synthesis to RTL Technology Libraries. DAC 1991: 526-529 | |
| 1990 | ||
| j1 | Nikil D. Dutt, Daniel D. Gajski: Design Synthesis and Silicon Compilation. IEEE Design & Test of Computers 7(6): 8-23 (1990) | |
| c3 | Nikil D. Dutt, Tedd Hadley, Daniel Gajski: An Intermediate Representation for Behavioral Synthesis. DAC 1990: 14-19 | |
| c2 | ||
| 1989 | ||
| c1 | ||
Colors in the list of coauthors
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