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Haakon Dybdahl

2000 – 2009

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2007
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Haakon Dybdahl, Per Stenström, Lasse Natvig: An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches. SIGARCH Computer Architecture News 35(4): 45-52 (2007)
[c4]
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Haakon Dybdahl, Per Stenström: An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors. HPCA 2007: 2-12
2006
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Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Grannæs, Lasse Natvig: Destructive-read in embedded DRAM, impact on power consumption. J. Embedded Computing 2(2): 249-260 (2006)
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Haakon Dybdahl, Per Stenström: Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination. Asia-Pacific Computer Systems Architecture Conference 2006: 52-66
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Haakon Dybdahl, Marius Grannæs, Lasse Natvig: Cache Write-Back Schemes for Embedded Destructive-Read DRAM. ARCS 2006: 145-159
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Haakon Dybdahl, Per Stenström, Lasse Natvig: A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors. HiPC 2006: 22-34

Coauthor Index

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What is the meaning of the colors in the coauthor index?