Stephan Eggersglüß

Stephan Eggersglüß, Rolf Drechsler: High Quality Test Pattern Generation and Boolean Satisfiability. Springer 2012, isbn 978-1-4419-9975-7, pp. I-XVIII, 1-193

Stephan Eggersglüß, Rolf Drechsler: A Highly Fault-Efficient SAT-Based ATPG Flow. IEEE Design & Test of Computers 29(4): 63-70 (2012)

Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty: Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization. ATS 2012: 290-295

Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler: A new SAT-based ATPG for generating highly compacted test sets. DDECS 2012: 230-235

Stephan Eggersglüß, Rolf Drechsler: Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. IEEE Trans. on CAD of Integrated Circuits and Systems 30(9): 1411-1415 (2011)

Stephan Eggersglüß, Rolf Drechsler: As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. DATE 2011: 1291-1296

Stephan Eggersglüß: Robust algorithms for high quality test pattern generation using Boolean satisfiability. University of Bremen 2010, pp. 1-182

Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler: MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electronic Testing 26(3): 307-322 (2010)

Daniel Tille, Stephan Eggersglüß, Rolf Drechsler: Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1125-1130 (2010)

Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler: Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. European Test Symposium 2010: 176-181

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler: Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS 2010: 649-652

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille: Test Pattern Generation using Boolean Proof Engines. Springer 2009, isbn 978-90-481-2359-9, pp. I-XII, 1-192

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille: Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it - Information Technology 51(2): 102-111 (2009)

Stephan Eggersglüß, Daniel Tille, Rolf Drechsler: Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium 2009: 177-182

Stephan Eggersglüß, Rolf Drechsler: Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. European Test Symposium 2009: 81-86

Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler: Timing Arc based logic analysis for false noise reduction. ICCAD 2009: 225-230

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille: On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008)

Stephan Eggersglüß, Rolf Drechsler: On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ISMVL 2008: 94-99

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler: SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674

Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6

Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler: Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV 2007: 81-90

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93