William Eklow
List of publications from the DBLP Bibliography Server - FAQ| 2013 | ||
|---|---|---|
| j4 | Li Jiang, Qiang Xu, Bill Eklow: On Effective Through-Silicon Via Repair for 3-D-Stacked ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 32(4): 559-571 (2013) | |
| 2012 | ||
| j3 | Bill Eklow: Managing Complex Boundary-Scan Operations. IEEE Design & Test of Computers 29(2): 100-102 (2012) | |
| c26 | Qiang Xu, Li Jiang, Huiyun Li, Bill Eklow: Yield enhancement for 3D-stacked ICs: Recent advances and challenges. ASP-DAC 2012: 731-737 | |
| c25 | ||
| c24 | Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson: Re-using chip level DFT at board level. European Test Symposium 2012: 1 | |
| c23 | Shahrzad Mirkhani, Jacob A. Abraham, Toai Vo, Hong Shin Jun, Bill Eklow: FALCON: Rapid statistical fault coverage estimation for complex designs. ITC 2012: 1-10 | |
| 2011 | ||
| j2 | Bill Eklow: Major Milestones for Two IEEE Standards Groups in 2011. IEEE Design & Test of Computers 28(6): 85-87 (2011) | |
| e2 | Bill Eklow, R. D. (Shawn) Blanton (Eds.): 2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011. IEEE 2011, isbn 978-1-4577-0153-5 | |
| 2009 | ||
| c22 | Luca Amati, Cristiana Bolchini, Laura Frigerio, Fabio Salice, William Eklow, Arnold Suvatne, Eugenio Brambilla, Federico Franzoso, Michele Martin: An Incremental Approach to Functional Diagnosis. DFT 2009: 392-400 | |
| e1 | Gordon W. Roberts, Bill Eklow (Eds.): 2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009. IEEE 2009, isbn 978-1-4244-4868-5 | |
| 2008 | ||
| c21 | ||
| c20 | ||
| 2006 | ||
| c19 | Bill Eklow, Ben Bennetts: New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG). European Test Symposium 2006: 253-254 | |
| c18 | Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, J.-F. Cote: IEEE P1687: Toward Standardized Access of Embedded Instrumentation. ITC 2006: 1-8 | |
| c17 | Sylvain Tourangeau, Bill Eklow: Test Economics - What can a Board/System Test Engineer do to Influence Supply Operation Metrics. ITC 2006: 1-9 | |
| 2005 | ||
| c16 | Zoe Conroy, Geoff Richmond, Xinli Gu, Bill Eklow: A practical perspective on reducing ASIC NTFs. ITC 2005: 7 | |
| c15 | ||
| c14 | Carlos O'Farrill, Merouane Moakil-Chbany, Bill Eklow: Optimized reasoning-based diagnosis for non-random, board-level, production defects. ITC 2005: 7 | |
| c13 | Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts: IJTAG (internal JTAG): a step toward a DFT standard. ITC 2005: 8 | |
| 2004 | ||
| c12 | ||
| c11 | Stephen K. Sunter, Adam Osseiran, Adam Cron, Neil Jacobson, Dave Bonnett, Bill Eklow, Carl Barnhart, Ben Bennetts: Status of IEEE Testability Standards 1149.4, 1532 and 1149.6. DATE 2004: 1184-1191 | |
| c10 | Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski: Realizing High Test Quality Goals with Smart Test Resource Usage. ITC 2004: 525-533 | |
| c9 | Bill Eklow, Anoosh Hosseini, Chi Khuong, Shyam Pullela, Toai Vo, Hien Chau: Simulation Based System Level Fault Insertion Using Co-verification Tools. ITC 2004: 704-710 | |
| c8 | Sunil Kalidindi, Nghia Huynh, Bill Eklow, Josh Goldstein: "Real Life" System Testing of Networking Equipment. ITC 2004: 1072-1077 | |
| c7 | ||
| 2003 | ||
| j1 | Bill Eklow, Carl Barnhart, Kenneth P. Parker: IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks. IEEE Design & Test of Computers 20(5): 76-83 (2003) | |
| c6 | Bill Eklow, Carl Barnhart, Mike Ricchetti, Terry Borroz: IEEE 1149.6 - A Practical Perspective. ITC 2003: 494-502 | |
| 2002 | ||
| c5 | Bill Eklow, Carl Barnhart, Kenneth P. Parker: IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks. ITC 2002: 1056-1065 | |
| c4 | ||
| 2001 | ||
| c3 | William Eklow, Richard M. Sedmak, Dan Singletary, Toai Vo: Unsafe board states during PC-based boundary-scan testing. ITC 2001: 615-623 | |
| 1998 | ||
| c2 | Bulent I. Dervisoglu, Mike Ricchetti, William Eklow: Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard. ITC 1998: 980-989 | |
| 1994 | ||
| c1 | ||
Colors in the list of coauthors
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