Emmanuelle Encrenaz
List of publications from the DBLP Bibliography Server - FAQ
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 | 2012 | |
|---|---|---|
| c14 |      | Syed Hussein S. Alwi, Cécile Braunstein, Emmanuelle Encrenaz: An efficient refinement strategy exploiting component properties in a cegar process. FDL 2012: 27-34 |
| 2011 | ||
| j10 | | Souheib Baarir, Cécile Braunstein, Emmanuelle Encrenaz, Jean-Michel Ilié, Isabelle Mounier, Denis Poitrenaud, Sana Younès: Feasibility analysis for robustness quantification by symbolic model checking. Formal Methods in System Design 39(2): 165-184 (2011) |
| 2010 | ||
| j9 | | Vincent Beaudenon, Emmanuelle Encrenaz, Sami Taktak: Data decision diagrams for Promela systems analysis. STTT 12(5): 337-352 (2010) |
| c13 |  | Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Ledu, Emmanuelle Encrenaz, Patricia Renault: Formal Verification of Timed VHDL Programs. FDL 2010: 80-85 |
| c12 | | Sami Taktak, Emmanuelle Encrenaz, Jean Lou Desbarbieux: A Polynomial Algorithm to Prove Deadlock-Freeness of Wormhole Networks. PDP 2010: 121-128 |
| 2009 | ||
| j8 | | Emmanuelle Encrenaz, Alain Finkel: Automatic Verification of Counter Systems With Ranking Function. Electr. Notes Theor. Comput. Sci. 239: 85-103 (2009) |
| j7 | | Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu: Timed verification of the generic architecture of a memory circuit using parametric timed automata. Formal Methods in System Design 34(1): 59-81 (2009) |
| j6 | | Étienne André, Thomas Chatain, Laurent Fribourg, Emmanuelle Encrenaz: An Inverse Method for Parametric Timed Automata. Int. J. Found. Comput. Sci. 20(5): 819-836 (2009) |
| c11 | | Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud: Complementary Formal Approaches for Dependability Analysis. DFT 2009: 331-339 |
| 2008 | ||
| j5 | | Emmanuelle Encrenaz, Laurent Fribourg: Time Separation of Events: An Inverse Method. Electr. Notes Theor. Comput. Sci. 209: 135-148 (2008) |
| j4 | | Étienne André, Thomas Chatain, Laurent Fribourg, Emmanuelle Encrenaz: An Inverse Method for Parametric Timed Automata. Electr. Notes Theor. Comput. Sci. 223: 29-46 (2008) |
| j3 | | Sami Taktak, Jean Lou Desbarbieux, Emmanuelle Encrenaz: A tool for automatic detection of deadlock in wormhole networks on chip. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008) |
| 2007 | ||
| j2 | | Cécile Braunstein, Emmanuelle Encrenaz: CTL-property Transformations along an Incremental Design Process. STTT 9(1): 77-88 (2007) |
| c10 | | Cécile Braunstein, Emmanuelle Encrenaz: Using CTL formulae as component abstraction in a design and verification flow. ACSD 2007: 80-89 |
| 2006 | ||
| c9 | | Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu: Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata. FORMATS 2006: 113-127 |
| c8 | | Sami Taktak, Emmanuelle Encrenaz, Jean Lou Desbarbieux: A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip. HLDVT 2006: 203-210 |
| c7 | | Cécile Braunstein, Emmanuelle Encrenaz: Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter. IEEE International Workshop on Rapid System Prototyping 2006: 103-109 |
| 2005 | ||
| j1 | | Cécile Braunstein, Emmanuelle Encrenaz: CTL-Property Transformations Along an Incremental Design Process. Electr. Notes Theor. Comput. Sci. 128(6): 263-278 (2005) |
| 2003 | ||
| c6 | | Vincent Beaudenon, Emmanuelle Encrenaz, Jean Lou Desbarbieux: Design Validation of ZCSP with SPIN. ACSD 2003: 102-110 |
| c5 | | Cédric Roux, Emmanuelle Encrenaz: CTL May Be Ambiguous When Model Checking Moore Machines. CHARME 2003: 164-169 |
| 2002 | ||
| c4 | | Jean-Michel Couvreur, Emmanuelle Encrenaz, Emmanuel Paviot-Adet, Denis Poitrenaud, Pierre-André Wacrenier: Data Decision Diagrams for Petri Net Analysis. ICATPN 2002: 101-120 |
| 1998 | ||
| c3 | | Fahim Rahim-Sarwary, Emmanuelle Encrenaz, Michel Minoux, Rajesh K. Bawa: Modular model checking of VLSI designs described in VHDL. Computers and Their Applications 1998: 368-371 |
| 1996 | ||
| c2 | | Rajesh K. Bawa, Emmanuelle Encrenaz: A Tool for Translation of VHDL Descriptions into a Formal Model and its Application to Formal Verification and Synthesis. FTRTFT 1996: 471-474 |
| 1995 | ||
| c1 | | Emmanuelle Encrenaz: A Symbolic Relation for a Subset of VHDL'87 Descriptions and its Application to Symbolic Model Checking. CHARME 1995: 328-342 |
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