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Milos D. Ercegovac
2010 – today
- 2012
[j39]Dong Wang, Milos D. Ercegovac: A Radix-16 Combined Complex Division/Square Root Unit with Operand Prescaling. IEEE Trans. Computers 61(9): 1243-1255 (2012)- [c60]Nicolas Brisebarre, Milos D. Ercegovac, Jean-Michel Muller: (M, p, k)-Friendly Points: A Table-Based Method for Trigonometric Function Evaluation. ASAP 2012: 46-52
- 2011
- [j38]Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac: Trading Accuracy for Power in a Multiplier Architecture. J. Low Power Electronics 7(4): 490-501 (2011)
- [c59]Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac: Trading Accuracy for Power with an Underdesigned Multiplier Architecture. VLSI Design 2011: 346-351
- [e1]Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca (Eds.): 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011. IEEE 2011, ISBN 978-1-4577-1291-3
- 2010
- [j37]Dong Wang, Milos D. Ercegovac, Nanning Zheng: Design of High-Throughput Fixed-Point Complex Reciprocal/Square-Root Unit. IEEE Trans. on Circuits and Systems 57-II(8): 627-631 (2010)
- [j36]Milos D. Ercegovac, Jean-Michel Muller: An Efficient Method for Evaluating Complex Polynomials. Signal Processing Systems 58(1): 17-27 (2010)
- [c58]Nicolas Brisebarre, Nicolas Louvet, Érik Martin-Dorel, Jean-Michel Muller, Adrien Panhaleux, Milos D. Ercegovac: Implementing decimal floating-point arithmetic through binary: Some suggestions. ASAP 2010: 317-320
- [i1]Jean-Claude Bajard, Sylvain Duquesne, Milos D. Ercegovac: Combining leak-resistant arithmetic for elliptic curves defined over Fp and RNS representation. IACR Cryptology ePrint Archive 2010: 311 (2010)
2000 – 2009
- 2009
- [j35]Sanghoon Kwak, Jeong-Gun Lee, Eun-Gu Jung, Dongsoo Har, Milos D. Ercegovac, Jeong-A. Lee: Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming. Journal of Circuits, Systems, and Computers 18(4): 787-800 (2009)
- [c57]Pouya Dormiani, Milos D. Ercegovac, Jean-Michel Muller: Design and Implementation of a Radix-4 Complex Division Unit with Prescaling. ASAP 2009: 83-90
- [c56]Dong Wang, Milos D. Ercegovac, Nanning Zheng: A radix-8 complex divider for FPGA implementation. FPL 2009: 236-241
- 2008
- [c55]Nicolas Brisebarre, Sylvain Chevillard, Milos D. Ercegovac, Jean-Michel Muller, Serge Torres: An efficient method for evaluating polynomial and rational function approximations. ASAP 2008: 233-238
- [p1]Florent de Dinechin, Milos D. Ercegovac, Jean-Michel Muller, Nathalie Revol: Digital Arithmetic. Wiley Encyclopedia of Computer Science and Engineering 2008
- 2007
- [j34]Milos D. Ercegovac, Jean-Michel Muller: Complex Square Root with Operand Prescaling. VLSI Signal Processing 49(1): 19-30 (2007)
- [c54]Milos D. Ercegovac, Jean-Michel Muller: A Hardware-Oriented Method for Evaluating Complex Polynomials. ASAP 2007: 122-127
- [c53]Jeong-Gun Lee, Jeong-A. Lee, Byeong-Seok Lee, Milos D. Ercegovac: A Design Method for Heterogeneous Adders. ICESS 2007: 121-132
- 2005
- [j33]Zhijun Huang, Milos D. Ercegovac: High-Performance Low-Power Left-to-Right Array Multiplier Design. IEEE Trans. Computers 54(3): 272-283 (2005)
- [j32]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. VLSI Signal Processing 40(1): 109-123 (2005)
- [c52]Pavan Adharapurapu, Milos D. Ercegovac: A Linear-System Operator Based Scheme for Evaluation of Multinomials. IEEE Symposium on Computer Arithmetic 2005: 249-256
- [c51]Milos D. Ercegovac, Jean-Michel Muller: Variable Radix Real and Complex Digit-Recurrence Division. ASAP 2005: 316-321
- [c50]Robert McIlhenny, Milos D. Ercegovac: RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions. FCCM 2005: 275-276
- 2004
- [j31]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. IEEE Trans. Computers 53(9): 1085-1096 (2004)
- [c49]Milos D. Ercegovac, Jean-Michel Muller: Complex Square Root with Operand Prescaling. ASAP 2004: 52-62
- [c48]David A. Rennels, Milos D. Ercegovac: From the University of Illinois via JPL and UCLA to Vytautas Magnus University - 50 years of computer engineering by Algirdas Avizienis. IFIP Congress Topical Sessions 2004: 175-190
- 2003
- [j30]Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1424-1431 (2003)
- [c47]Zhijun Huang, Milos D. Ercegovac: High-Performance Left-to-Right Array Multiplier Design. IEEE Symposium on Computer Arithmetic 2003: 4-11
- [c46]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: High-Radix Iterative Algorithm for Powering Computation. IEEE Symposium on Computer Arithmetic 2003: 204-211
- [c45]José-Alejandro Piñeiro, Javier D. Bruguera, Milos D. Ercegovac: On-line high-radix exponential with selection by rounding. ISCAS (4) 2003: 121-124
- 2002
- [c44]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: High-Radix Logarithm with Selection by Rounding. ASAP 2002: 101-110
- [c43]José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera: Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. ICCD 2002: 132-137
- [c42]Zhijun Huang, Milos D. Ercegovac: Two-dimensional signal gating for low-power array multiplier design. ISCAS (1) 2002: 489-492
- [c41]Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac: High-Level Synthesis with SIMD Units. VLSI Design 2002: 407-413
- 2001
- [j29]Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor: A FPGA-based Library for On-Line Signal Processing. VLSI Signal Processing 28(1-2): 129-143 (2001)
- [c40]Zhijun Huang, Milos D. Ercegovac: FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization. FCCM 2001: 61-70
- [c39]Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang: Performance-driven mapping for CPLD architectures. FPGA 2001: 39-47
- 2000
- [j28]Milos D. Ercegovac, Tomás Lang, Jean-Michel Muller, Arnaud Tisserand: Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers. IEEE Trans. Computers 49(7): 628-637 (2000)
- [j27]Milos D. Ercegovac, Laurent Imbert, David W. Matula, Jean-Michel Muller, Guoheng Wei: Improving Goldschmidt Division, Square Root, and Square Root Reciprocal. IEEE Trans. Computers 49(7): 759-763 (2000)
- [c38]Aaron Schneider, Robert McIlhenny, Milos D. Ercegovac: BigSky-An On-Line Arithmetic Design Tool for FPGAs. FCCM 2000: 303-304
- [c37]Jeffrey M. Fischer, Milos D. Ercegovac: A Component Framework for Communication in Distributed Applications. IPDPS 2000: 647-654
1990 – 1999
- 1999
- [c36]Alexandre F. Tenca, Milos D. Ercegovac: On the Design of High-Radix On-Line Division for Long Precision. IEEE Symposium on Computer Arithmetic 1999: 44-51
- [c35]Milos D. Ercegovac, Darko Kirovski, Miodrag Potkonjak: Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic. DAC 1999: 568-573
- [c34]Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor: FPGA-Based Structures for On-Line FFT and DCT. FCCM 1999: 310-311
- 1998
- [j26]Mircea R. Stan, Alexandre F. Tenca, Milos D. Ercegovac: Long and Fast Up/Down Counters. IEEE Trans. Computers 47(7): 722-735 (1998)
- [c33]Alexandre F. Tenca, Milos D. Ercegovac: A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures. FCCM 1998: 216-225
- 1997
- [c32]Alexandre F. Tenca, Milos D. Ercegovac: Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size. FPGA 1997: 159-165
- 1996
- [j25]Raffi Dionysian, Milos D. Ercegovac: Vector quantization with variable-precision classification. IEEE Transactions on Image Processing 5(11): 1528-1538 (1996)
- [j24]Milos D. Ercegovac, Tomás Lang: On recoding in arithmetic algorithms. VLSI Signal Processing 14(3): 283-294 (1996)
- 1995
- [j23]Marianne E. Louie, Milos D. Ercegovac: A variable-precision square root implementation for field programmable gate arrays. The Journal of Supercomputing 9(3): 315-336 (1995)
- [c31]Milos D. Ercegovac, Tomás Lang: Sign detection and comparison networks with a small number of transitions. IEEE Symposium on Computer Arithmetic 1995: 59-66
- 1994
- [j22]Milos D. Ercegovac, Tomás Lang, Paolo Montuschi: Very-High Radix Division with Prescaling and Selection by Rounding. IEEE Trans. Computers 43(8): 909-918 (1994)
- [j21]John S. Fernando, Milos D. Ercegovac: Conventional and on-line arithmetic designs for high-speed recursive digital filters. VLSI Signal Processing 7(3): 189-197 (1994)
- [j20]Marianne E. Louie, Milos D. Ercegovac: Implementing division with field programmable gate arrays. VLSI Signal Processing 7(3): 271-285 (1994)
- 1993
- [j19]Milos D. Ercegovac, Tomás Lang: Multiplication/ division/ square root module for massively parallel computers. Integration 16(3): 221-234 (1993)
- [c30]Milos D. Ercegovac, Tomás Lang, Paolo Montuschi: Very high radix division with selection by rounding and prescaling. IEEE Symposium on Computer Arithmetic 1993: 112-119
- [c29]Marianne E. Louie, Milos D. Ercegovac: On digit-recurrence division implementations for field programmable gate arrays. IEEE Symposium on Computer Arithmetic 1993: 202-209
- [c28]James J. Liu, Milos D. Ercegovac: Symbolic Synthesis of Parallel Processing Systems. IPPS 1993: 496-500
- [c27]James J. Liu, Milos D. Ercegovac: ALIAS Environment: A Design Tool for Application Specific Arrays. SPDP 1993: 504-511
- 1992
- [j18]Leon Alkalaj, Tomás Lang, Milos D. Ercegovac: Architectural Support for Goal Management in Flat Concurrent Prolog. IEEE Computer 25(8): 34-47 (1992)
- [j17]Alex Kapelnikov, Richard R. Muntz, Milos D. Ercegovac: A Methodology for Performance Analysis of Parallel Compuations with Looping Constructs. J. Parallel Distrib. Comput. 14(2): 105-120 (1992)
- [j16]
- [c26]Raffi Dionysian, Milos D. Ercegovac: Variable Precision Representation for Efficient VQ Codebook Storage. Data Compression Conference 1992: 319-328
- 1991
- [j15]Milos D. Ercegovac, Tomás Lang: Module to Perform Multiplication, Division, and Square Root in Systolic Arrays for Matrix Computations. J. Parallel Distrib. Comput. 11(3): 212-221 (1991)
- [j14]Paul K.-G. Tu, Milos D. Ercegovac: Gate array implementation of on-line algorithms for floating-point operations. VLSI Signal Processing 3(4): 307-317 (1991)
- [c25]Paul K.-G. Tu, Milos D. Ercegovac: Application of on-line arithmetic algorithms to the SVD computation: preliminary results. IEEE Symposium on Computer Arithmetic 1991: 246-255
- 1990
- [j13]Milos D. Ercegovac, Tomás Lang: Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD. IEEE Trans. Computers 39(6): 725-740 (1990)
- [j12]Milos D. Ercegovac, Tomás Lang: Radix-4 Square Root Without Initial PLA. IEEE Trans. Computers 39(8): 1016-1024 (1990)
- [j11]Milos D. Ercegovac, Tomás Lang: Simple Radix-4 Division with Opterands Scaling. IEEE Trans. Computers 39(9): 1204-1208 (1990)
- [j10]Milos D. Ercegovac, Tomás Lang: Fast Multiplication Without Carry-Propagate Addition. IEEE Trans. Computers 39(11): 1385-1390 (1990)
- [c24]Leon Alkalaj, Tomás Lang, Milos D. Ercegovac: Architectural Support for the Management of Tightly-Coupled Fine-Grain Goals in Flat Concurrent Prolog. ISCA 1990: 292-301
1980 – 1989
- 1989
- [j9]Alex Kapelnikov, Richard R. Muntz, Milos D. Ercegovac: A Modeling Methodology for the Analysis of Concurrent Systems and Computations. J. Parallel Distrib. Comput. 6(3): 568-597 (1989)
- [c23]Ralph Hans Brackert Jr., Milos D. Ercegovac, Alan N. Willson Jr.: Design of an on-line multiply-add module for recursive digital filters. IEEE Symposium on Computer Arithmetic 1989: 34-41
- [c22]Paul K.-G. Tu, Milos D. Ercegovac: Design of on-line division unit. IEEE Symposium on Computer Arithmetic 1989: 42-49
- [c21]Milos D. Ercegovac, Tomás Lang: Radix-4 square root without initial PLA. IEEE Symposium on Computer Arithmetic 1989: 162-168
- [c20]Milos D. Ercegovac, Tomás Lang: On-the-fly rounding for division and square root. IEEE Symposium on Computer Arithmetic 1989: 169-173
- 1988
- [j8]Milos D. Ercegovac, Tomás Lang: On-Line Scheme for Computing Rotation Factors. J. Parallel Distrib. Comput. 5(3): 209-227 (1988)
- [j7]Milos D. Ercegovac: Heterogeneity in supercomputer architectures. Parallel Computing 7(3): 367-372 (1988)
- 1987
- [j6]Milos D. Ercegovac, Tomás Lang: On-the-Fly Conversion of Redundant into Conventional Representations. IEEE Trans. Computers 36(7): 895-897 (1987)
- [c19]Paul K.-G. Tu, Milos D. Ercegovac: A radix-4 on-line division algorithm. IEEE Symposium on Computer Arithmetic 1987: 181-187
- [c18]Milos D. Ercegovac, Tomás Lang: On-line scheme for computing rotation factors. IEEE Symposium on Computer Arithmetic 1987: 196-203
- 1985
- [c17]Milos D. Ercegovac, Tomás Lang: A division algorithm with prediction of quotient digits. IEEE Symposium on Computer Arithmetic 1985: 51-56
- [c16]F. Meshkinpour, Milos D. Ercegovac: A functional language for description and design of digital systems: sequential constructs. DAC 1985: 238-244
- [c15]Dorab Patel, Martine D. F. Schlag, Milos D. Ercegovac: vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms. FPCA 1985: 238-255
- 1984
- [j5]Cauligi S. Raghavendra, Algirdas Avizienis, Milos D. Ercegovac: Fault Tolerance in Binary Tree Architectures. IEEE Trans. Computers 33(6): 568-572 (1984)
- [c14]Jean-Luc Gaudiot, Milos D. Ercegovac: Performance Analysis of a Data-Flow Computer with Variable Resolution Actors. ICDCS 1984: 2-9
- 1983
- [j4]Osaaki Watanuki, Milos D. Ercegovac: Error Analysis of Certain Floating-Point On-Line Algorithms. IEEE Trans. Computers 32(4): 352-358 (1983)
- [c13]Milos D. Ercegovac: A higher-radix division with simple selection of quotient digits. IEEE Symposium on Computer Arithmetic 1983: 94-98
- [c12]Aksenti L. Grnarov, Milos D. Ercegovac: On-line multiplicative normalization. IEEE Symposium on Computer Arithmetic 1983: 151-155
- 1982
- [j3]Vojin G. Oklobdzija, Milos D. Ercegovac: A On-Line Square Root Algorithm. IEEE Trans. Computers 31(1): 70-75 (1982)
- [c11]Jean-Luc Gaudiot, Milos D. Ercegovac: A scheme for handling arrays in data-flow systems. ICDCS 1982: 724-729
- 1981
- [c10]Abdolali Gorji-Sinaki, Milos D. Ercegovac: Design of a digit-slice on-line arithmetic unit. IEEE Symposium on Computer Arithmetic 1981: 72-80
- [c9]Osaaki Watanuki, Milos D. Ercegovac: Floating-point on-line arithmetic: Algorithms. IEEE Symposium on Computer Arithmetic 1981: 81-86
- [c8]Osaaki Watanuki, Milos D. Ercegovac: Floating-point on-line arithmetic: Error analysis. IEEE Symposium on Computer Arithmetic 1981: 87-91
- [c7]Cauligi S. Raghavendra, Milos D. Ercegovac: A simulator for on-line arithmetic. IEEE Symposium on Computer Arithmetic 1981: 92-98
- [c6]M. Feller, Milos D. Ercegovac: Queue machines: an organization for parallel computation. CONPAR 1981: 37-47
1970 – 1979
- 1978
- [c5]Milos D. Ercegovac: An on-line square rooting algorithm. IEEE Symposium on Computer Arithmetic 1978: 183-189
- [c4]Milos D. Ercegovac, Melvin M. Takata: An arithmetic module for efficient evaluation of functions. IEEE Symposium on Computer Arithmetic 1978: 190-199
- 1977
- [j2]Milos D. Ercegovac: A General Hardware-Oriented Method for Evaluation of Functions and Computations in a Digital Computer. IEEE Trans. Computers 26(7): 667-680 (1977)
- [j1]Kishor S. Trivedi, Milos D. Ercegovac: On-Line Algorithms for Division and Multiplication. IEEE Trans. Computers 26(7): 681-687 (1977)
- 1975
- [c3]Milos D. Ercegovac: A general method for evaluation of functions and computations in a digital computing. IEEE Symposium on Computer Arithmetic 1975: 147-157
- [c2]Kishor S. Trivedi, Milos D. Ercegovac: On-line algorithms for division and multiplication. IEEE Symposium on Computer Arithmetic 1975: 161-167
- 1972
- [c1]Milos D. Ercegovac: Eadix l6 evaluation of some elementary functions. IEEE Symposium on Computer Arithmetic 1972: 1-25
Coauthor Index
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last updated on 2012-12-02 21:23 CET by the dblp team