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 | 2013 | |
|---|---|---|
| j9 |      | Kristof Du Bois, Stijn Eyerman, Lieven Eeckhout: Per-thread cycle accounting in multicore processors. TACO 9(4): 29 (2013) |
| 2012 | ||
| j8 | | Stijn Eyerman, Lieven Eeckhout: Probabilistic modeling for job symbiosis scheduling on SMT processors. TACO 9(2): 7 (2012) |
| c17 | | Osman Allam, Stijn Eyerman, Lieven Eeckhout: An efficient CPI stack counter architecture for superscalar processors. ACM Great Lakes Symposium on VLSI 2012: 55-58 |
| c16 | | Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy Kurian John: A first-order mechanistic model for architectural vulnerability factor. ISCA 2012: 273-284 |
| c15 | | Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout: A mechanistic performance model for superscalar in-order processors. ISPASS 2012: 14-24 |
| c14 | | Stijn Eyerman, Kristof Du Bois, Lieven Eeckhout: Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications. ISPASS 2012: 145-155 |
| 2011 | ||
| j7 | | |
| c13 | | Stijn Eyerman, Kenneth Hoste, Lieven Eeckhout: Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware. ISPASS 2011: 216-226 |
| c12 | | Maximilien Breughe, Zheng Li, Yang Chen, Stijn Eyerman, Olivier Temam, Chengyong Wu, Lieven Eeckhout: How sensitive is processor customization to the workload's input datasets? SASP 2011: 1-7 |
| 2010 | ||
| j6 | | |
| j5 | | Stijn Eyerman, Lieven Eeckhout: A Counter Architecture for Online DVFS Profitability Estimation. IEEE Trans. Computers 59(11): 1576-1583 (2010) |
| c11 | | Stijn Eyerman, Lieven Eeckhout: Probabilistic job symbiosis modeling for SMT processor scheduling. ASPLOS 2010: 91-102 |
| c10 | | Davy Genbrugge, Stijn Eyerman, Lieven Eeckhout: Interval simulation: Raising the level of abstraction in architectural simulation. HPCA 2010: 1-12 |
| c9 | | Stijn Eyerman, Lieven Eeckhout: Modeling critical sections in Amdahl's law and its implications for multicore design. ISCA 2010: 362-370 |
| 2009 | ||
| j4 | | Stijn Eyerman, Lieven Eeckhout: Memory-level parallelism aware fetch policies for simultaneous multithreading processors. TACO 6(1) (2009) |
| j3 | | Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith: A mechanistic performance model for superscalar out-of-order processors. ACM Trans. Comput. Syst. 27(2) (2009) |
| c8 | | |
| c7 | | Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout: MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor. HiPEAC 2009: 110-124 |
| 2008 | ||
| j2 | | Stijn Eyerman, Lieven Eeckhout: System-Level Performance Metrics for Multiprogram Workloads. IEEE Micro 28(3): 42-53 (2008) |
| c6 | | Stijn Eyerman, Lieven Eeckhout, James E. Smith: Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. HiPEAC 2008: 114-129 |
| 2007 | ||
| j1 | | Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith: A Top-Down Approach to Architecting CPI Component Performance Counters. IEEE Micro 27(1): 84-93 (2007) |
| c5 | | Stijn Eyerman, Lieven Eeckhout, James E. Smith: Studying Compiler-Microarchitecture Interactions through Interval Analysis. PACT 2007: 406 |
| c4 | | Stijn Eyerman, Lieven Eeckhout: A Memory-Level Parallelism Aware Fetch Policy for SMT Processors. HPCA 2007: 240-249 |
| 2006 | ||
| c3 | | Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith: A performance counter architecture for computing accurate CPI components. ASPLOS 2006: 175-184 |
| c2 | | Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere: Efficient design space exploration of high performance embedded out-of-order processors. DATE 2006: 351-356 |
| c1 | | Stijn Eyerman, James E. Smith, Lieven Eeckhout: Characterizing the branch misprediction penalty. ISPASS 2006: 48-58 |
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