| 2013 | ||
|---|---|---|
| j7 | Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang: Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS. IEICE Transactions 96-A(5): 963-970 (2013) | |
| 2012 | ||
| j6 | Weiwei Shen, Yibo Fan, Xiaoyang Zeng: A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K × 2 K Applications. IEICE Transactions 95-C(4): 441-446 (2012) | |
| j5 | Yibo Fan, Jialiang Liu, Dexue Zhang, Xiaoyang Zeng, Xinhua Chen: An 8 × 4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4 K × 2 K H.264/AVC Encoder. IEICE Transactions 95-C(4): 447-455 (2012) | |
| c10 | Huailu Ren, Yibo Fan, Xinhua Chen, Xiaoyang Zeng: A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder. ASP-DAC 2012: 801-806 | |
| c9 | Sha Shen, Weiwei Shen, Yibo Fan, Xiaoyang Zeng: A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards. ICME 2012: 788-793 | |
| c8 | Huibo Zhong, Yibo Fan, Xiaoyang Zeng: A parallel CAVLC design for 4096×2160p encoder. ISCAS 2012: 1432-1435 | |
| c7 | Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng: A Low Complexity Macroblock Layer Rate Control Scheme Base on Weighted-Window for H.264 Encoder. MMM 2012: 563-573 | |
| 2011 | ||
| j4 | Yibo Fan, Xiaoyang Zeng, Satoshi Goto: Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC. IEICE Transactions 94-C(4): 411-418 (2011) | |
| c6 | Jiang Ying, Xinhua Chen, Yibo Fan, Xiaoyang Zeng: MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder. VLSI-SoC 2011: 72-77 | |
| c5 | Jialiang Liu, Xinhua Chen, Yibo Fan, Xiaoyang Zeng: A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder. VLSI-SoC 2011: 434-439 | |
| 2008 | ||
| j3 | Yibo Fan, Jidong Wang, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto: An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard. IEICE Transactions 91-A(1): 12-21 (2008) | |
| j2 | Yibo Fan, Takeshi Ikenaga, Satoshi Goto: Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm. IEICE Transactions 91-C(4): 440-448 (2008) | |
| j1 | Yibo Fan, Takeshi Ikenaga, Satoshi Goto: A High-Speed Design of Montgomery Multiplier. IEICE Transactions 91-A(4): 971-977 (2008) | |
| 2007 | ||
| c4 | Yibo Fan, Jidong Wang, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto: A New Video Encryption Scheme for H.264/AVC. PCM 2007: 246-255 | |
| 2006 | ||
| c3 | Min Wu, Xiaoyang Zeng, Jun Han, Yongyi Wu, Yibo Fan: A high-performance platform-based SoC for information security. ASP-DAC 2006: 122-123 | |
| c2 | Yibo Fan, Xiaoyang Zeng, Yu Yu, Gang Wang, Qianling Zhang: A modified high-radix scalable Montgomery multiplier. ISCAS 2006 | |
| 2005 | ||
| c1 | Yibo Fan, Xiaoyang Zeng, Zhang Zhang, Jun Chen, Qianling Zhang: VLSI design of a high-speed RAS crypto-processor with reconfigurable architecture. ISSPA 2005: 307-310 | |
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