- CSB - MetaPress - Google - Bing - Yahoo
 | 2013 | |
|---|---|---|
| c17 |      | Nuno Paulino, João Canas Ferreira, João M. P. Cardoso: Architecture for Transparent Binary Acceleration of Loops with Memory Accesses. ARC 2013: 122-133 |
| 2012 | ||
| j4 | | Miguel Lino Silva, João Canas Ferreira: Run-time generation of partial FPGA configurations. Journal of Systems Architecture - Embedded Systems Design 58(1): 24-37 (2012) |
| j3 | | Miguel Lino Silva, João Canas Ferreira: Run-time generation of partial FPGA configurations for subword operations. Microprocessors and Microsystems - Embedded Hardware Design 36(5): 365-374 (2012) |
| c16 | | Ali Azarian, João Canas Ferreira, Stephan Werner, Zlatko Petrov, João M. P. Cardoso, Michael Hübner: Analysis of error detection schemes: Toolchain support and hardware/software implications. AHS 2012: 62-69 |
| c15 | | Fardin Derogarian, João Canas Ferreira, Vitor M. Grade Tavares: Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks. DSD 2012: 896-901 |
| c14 | | Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira: A scalable array for Cellular Genetic Algorithms: TSP as case study. ReConFig 2012: 1-6 |
| 2011 | ||
| c13 | | João Bispo, Nuno Paulino, João M. P. Cardoso, João Canas Ferreira: From Instruction Traces to Specialized Reconfigurable Arrays. ReConFig 2011: 386-391 |
| 2010 | ||
| c12 | | Joao G. P. Rodrigues, João Canas Ferreira: FPGA-based rectification of stereo images. DASIP 2010: 199-206 |
| c11 | | Miguel Lino Silva, João Canas Ferreira: Creation of Partial FPGA Configurations at Run-Time. DSD 2010: 80-87 |
| c10 | | |
| 2008 | ||
| c9 | | Miguel Lino Silva, João Canas Ferreira: Generation of partial FPGA configurations at run-time. FPL 2008: 367-372 |
| 2007 | ||
| j2 | | Miguel Lino Silva, João Canas Ferreira: Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems. IET Computers & Digital Techniques 1(5): 461-471 (2007) |
| 2006 | ||
| j1 | | Miguel Lino Silva, João Canas Ferreira: Support for partial run-time reconfiguration of platform FPGAs. Journal of Systems Architecture 52(12): 709-726 (2006) |
| 2005 | ||
| c8 | | Miguel Lino Silva, João Canas Ferreira: Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. DSD 2005: 383-387 |
| c7 | | João Canas Ferreira, Miguel M. Silva: Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer. IPDPS 2005 |
| 2004 | ||
| c6 | | João Canas Ferreira, José Silva Matos: A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. FPL 2004: 886-890 |
| 1999 | ||
| c5 | | José Carlos Alves, João Canas Ferreira, C. Albuquerque, José F. Oliveira, J. Soeiro Ferreira, José Silva Matos: FAFNER-Accelerating Nesting Problems with FPGAs. FCCM 1999: 168- |
| 1998 | ||
| c4 | | João Canas Ferreira, José Silva Matos: A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. FCCM 1998: 280-281 |
| 1994 | ||
| c3 |  | José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva: An Approach to Testability Improvement of Mixed-Signal Boards. ISCAS 1994: 161-164 |
| c2 | | José Silva Matos, João Canas Ferreira, Ana C. Leão, J. Machado Silva: Architecture of test support ICs for mixed-signal testing. VTS 1994: 240-246 |
| 1993 | ||
| c1 | | José Silva Matos, Ana C. Leão, João Canas Ferreira: Control and Observation of Analog Nodes in Mixed-Signal Boards. ITC 1993: 323-331 |
Colors in the list of coauthors
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