Görschwin Fey

Mehdi Dehbashi, André Sülflow, Görschwin Fey: Automated design debugging in a testbench-based verification environment. Microprocessors and Microsystems - Embedded Hardware Design 37(2): 206-217 (2013)

Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda: Reliability analysis reloaded: how will we survive? DATE 2013: 358-367

Heinz Riener, Stefan Frehse, Görschwin Fey: Improving fault tolerance utilizing hardware-software-co-synthesis. DATE 2013: 939-942

Jan Malburg, Alexander Finder, Görschwin Fey: Tuning dynamic data flow analysis to support design understanding. DATE 2013: 1179-1184

Heinz Riener, Görschwin Fey: Yet a Better Error Explanation Algorithm (Extended Abstract). MBMV 2013: 193-194

Mehdi Dehbashi, Görschwin Fey: Automated Post-Silicon Debugging of Failing Speedpaths. ATS 2012: 13-18

Jan Malburg, Alexander Finder, Görschwin Fey: Automated feature localization for hardware designs using coverage metrics. DAC 2012: 941-946

Mehdi Dehbashi, Görschwin Fey: Automated debugging from pre-silicon to post-silicon. DDECS 2012: 324-329

Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan: On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD 2012: 431-436

Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan: Functional analysis of circuits under timing variations. European Test Symposium 2012: 1

Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler: Complete and effective robustness checking by means of interpolation. FMCAD 2012: 82-90

Jan Malburg, Alexander Finder, Görschwin Fey: Automated Feature Localization for Hardware Designs using Coverage Metrics. MBMV 2012: 85-96

Heinz Riener, Görschwin Fey: Model-based diagnosis versus error explanation. MEMOCODE 2012: 43-52

Heinz Riener, Görschwin Fey: FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation. SPIN 2012: 234-240

Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda: Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports 2(8): 57-73 (2012)

Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler: Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1239-1252 (2011)

Görschwin Fey: Orchestrated multi-level information flow analysis to understand SoCs. DAC 2011: 284-285

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler: Automatic property generation for the formal verification of bus bridges. DDECS 2011: 417-422

Mehdi Dehbashi, André Sülflow, Görschwin Fey: Automated Design Debugging in a Testbench-Based Verification Environment. DSD 2011: 479-486

Alexander Finder, André Sülflow, Görschwin Fey: Latency Analysis for Sequential Circuits. European Test Symposium 2011: 129-134

Heinz Riener, Roderick Bloem, Görschwin Fey: Test Case Generation from Mutants Using Model Checking Techniques. ICST Workshops 2011: 388-397

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler: Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV 2011: 183-192

Görschwin Fey: Assessing System Vulnerability Using Formal Verification Techniques. MEMICS 2011: 47-56

Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler: MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electronic Testing 26(3): 307-322 (2010)

Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler: Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it - Information Technology 52(4): 216-223 (2010)

Rolf Drechsler, Görschwin Fey: Formal verification meets robustness checking - Techniques and challenges. DDECS 2010: 4

Stefan Frehse, Görschwin Fey, Rolf Drechsler: A better-than-worst-case robustness measure. DDECS 2010: 78-83

Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler: RobuCheck: A Robustness Checker for Digital Circuits. DSD 2010: 226-231

Alexander Finder, Görschwin Fey: Evaluating Debugging Algorithms from a Qualitative Perspective. FDL 2010: 37-42

Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler: Polynomial datapath optimization using constraint solving and formal modelling. ICCAD 2010: 756-761

André Sülflow, Görschwin Fey, Rolf Drechsler: Using QBF to increase accuracy of SAT-based debugging. ISCAS 2010: 641-644

Görschwin Fey, André Sülflow, Rolf Drechsler: Towards Unifying Localization and Explanation for Automated Debugging. MTV 2010: 3-8

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille: Test Pattern Generation using Boolean Proof Engines. Springer 2009, isbn 978-90-481-2359-9, pp. I-XII, 1-192

Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Advanced verification by automatic property generation. IET Computers & Digital Techniques 3(4): 338-353 (2009)

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille: Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it - Information Technology 51(2): 102-111 (2009)

Görschwin Fey: Deterministic Algorithms for ATPG under Leakage Constraints. Asian Test Symposium 2009: 313-316

Görschwin Fey, André Sülflow, Rolf Drechsler: Computing bounds for fault tolerance using formal techniques. DAC 2009: 190-195

André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler: Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331

Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler: Robustness Check for Multiple Faults Using Formal Techniques. DSD 2009: 85-90

André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler: Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL 2009: 298-303

André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler: Increasing the Accuracy of SAT-based Debugging. MBMV 2009: 47-56

André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler: WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17

Görschwin Fey, Rolf Drechsler: Robustness and usability in modern design flows. Springer 2008, isbn 978-1-4020-6535-4, pp. I-XIII, 1-166

Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the construction of small fully testable circuits with low depth. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 263-269 (2008)

Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1138-1149 (2008)

Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille: On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008)

Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Automatic Generation of Complex Properties for Hardware Designs. DATE 2008: 545-548

Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler: Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD 2008: 542-549

André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI 2008: 77-82

Görschwin Fey, Rolf Drechsler: A Basis for Formal Robustness Checking. ISQED 2008: 784-789

André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Debugging Design Errors by Using Unsatisfiable Cores. MBMV 2008: 159-168

Daniel Tille, Görschwin Fey, Rolf Drechsler: Instance Generation for SAT-based ATPG. DDECS 2007: 153-156

Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler: On the Construction of Small Fully Testable Circuits with Low Depth. DSD 2007: 563-569

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler: SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674

Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6

Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler: Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV 2007: 81-90

André Sülflow, Görschwin Fey, Rolf Drechsler: Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. MBMV 2007: 101-110

Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187

Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93

Görschwin Fey, Tim Warode, Rolf Drechsler: Reusing Learned Information in SAT-based ATPG. VLSI Design 2007: 69-76

Görschwin Fey: Increasing robustness and usability of circuit design tools by using formal techniques. Universität Bremen 2006, pp. I-VIII, 1-164

Görschwin Fey, Rolf Drechsler: Minimizing the number of paths in BDDs: Theory and algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 4-11 (2006)

Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144

Görschwin Fey, Daniel Große, Rolf Drechsler: Avoiding false negatives in formal verification for protocol-driven blocks. DATE 2006: 1225-1226

Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler: Automatic Fault Localization for Property Checking. Haifa Verification Conference 2006: 50-64

Görschwin Fey, Junhao Shi, Rolf Drechsler: Efficiency of Multi-Valued Encoding in SAT-based ATPG. ISMVL 2006: 25

Görschwin Fey, Rolf Drechsler: SAT-based Calculation of Source Code Coverage for BMC. MBMV 2006: 163-170

Rolf Drechsler, Görschwin Fey: Automatic Test Pattern Generation. SFM 2006: 30-55

Rolf Drechsler, Görschwin Fey, Sebastian Kinder: An Integrated Approach for Combining BDD and SAT Provers. VLSI Design 2006: 237-242

Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler: Advanced BDD optimization. Springer 2005, isbn 978-0-387-25453-1, pp. I-X, 1-222

Junhao Shi, Görschwin Fey, Rolf Drechsler: Bridging fault testability of BDD circuits. ASP-DAC 2005: 188-191

Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler: Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269

Sebastian Kinder, Görschwin Fey, Rolf Drechsler: Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ISMVL 2005: 250-255

Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel: PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI 2005: 212-217

Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große: SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping 2005: 258-260

Rolf Drechsler, Junhao Shi, Görschwin Fey: Synthesis of fully testable circuits from BDDs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 440-443 (2004)

Görschwin Fey, Rolf Drechsler: Improving simulation-based verification by means of formal methods. ASP-DAC 2004: 640-643

Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey: Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. DATE 2004: 162-167

Görschwin Fey, Junhao Shi, Rolf Drechsler: BDD Circuit Optimization for Path Delay Fault Testability. DSD 2004: 168-172

Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler: Disjoint Sum of Product Minimization by Evolutionary Algorithms. EvoWorkshops 2004: 198-207

Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski: Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240

Junhao Shi, Görschwin Fey, Rolf Drechsler: BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium 2003: 290-293

Rolf Drechsler, Junhao Shi, Görschwin Fey: MuTaTe: an efficient design for testability technique for multiplexor based circuits. ACM Great Lakes Symposium on VLSI 2003: 80-83

Daniel Große, Görschwin Fey, Rolf Drechsler: Modeling Multi-Valued Circuits in SystemC. ISMVL 2003: 281-286

Görschwin Fey, Sebastian Kinder, Rolf Drechsler: Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. ISMVL 2003: 361-366

Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey: Cost-efficient Formal Block Verification for ASIC Design. MBMV 2003: 184-188

Görschwin Fey, Rolf Drechsler: Finding Good Counter-Examples to Aid Design Verification. MEMOCODE 2003: 51-