Petr Fiser

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	2013
j3		Jiri Balcarek, Petr Fiser, Jan Schmidt: Techniques for SAT-based constrained test pattern generation. Microprocessors and Microsystems - Embedded Hardware Design 37(2): 185-195 (2013)
	2012
c21		Petr Fiser, Jan Schmidt: Improving the iterative power of resynthesis. DDECS 2012: 30-33
c20		Jan Schmidt, Petr Fiser, Jiri Balcarek: The Influence of Implementation Technology on Dependability Parameters. DSD 2012: 368-373
	2011
c19		Jiri Balcarek, Petr Fiser, Jan Schmidt: Techniques for SAT-Based Constrained Test Pattern Generation. DSD 2011: 360-366
	2010
c18		Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina: On logic synthesis of conventionally hard to synthesize circuits using genetic programming. DDECS 2010: 346-351
c17		Igor Lemberski, Petr Fiser: Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. DSD 2010: 155-162
c16		Jiri Balcarek, Petr Fiser, Jan Schmidt: Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. DSD 2010: 805-808
	2009
c15		Igor Lemberski, Petr Fiser: Asynchronous two-level logic of reduced cost. DDECS 2009: 68-73
c14		Jan Schmidt, Petr Fiser: The Case for a Balanced Decomposition Process. DSD 2009: 601-604
c13		Petr Fiser, David Toman: A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms. DSD 2009: 757-764
	2008
j2		Petr Fiser, Hana Kubatova: Column-matching based mixed-mode test pattern generator design technique for BIST. Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 340-350 (2008)
c12		Petr Fiser, Pemysl Rucký, Irena Vanová: Fast Boolean Minimizer for Completely Specified Functions. DDECS 2008: 122-127
c11		Petr Fiser, Pavel Kubalík, Hana Kubatova: An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. DSD 2008: 96-99
	2007
c10		Petr Fiser: Pseudo-Random Pattern Generator Design for Column-Matching BIST. DSD 2007: 657-663
	2006
c9		Petr Fiser, Hana Kubatova: Multiple-Vector Column-Matching BIST Design Method. DDECS 2006: 268-273
c8		Petr Fiser, Hana Kubatova: Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications. DSD 2006: 369-376
c7		Pavel Kubalík, Petr Fiser, Hana Kubatova: Fault Tolerant System Design Method Based on Self-Checking Circuits. IOLTS 2006: 185-186
	2004
c6		Petr Fiser, Hana Kubatova: Boolean Minimizer FC-Min: Coverage Finding Process. DSD 2004: 152-159
c5		Petr Fiser, Hana Kubatova: Survey of the Algorithms in the Column-Matching BIST Method. IOLTS 2004: 181
	2003
j1		Jan Hlavicka, Petr Fiser: BOOM - A Heuristic Boolean Minimizer. Computers and Artificial Intelligence 22(1): 19-51 (2003)
c4		Petr Fiser, Jan Hlavicka, Hana Kubatova: FC-Min: A Fast Multi-Output Boolean Minimizer. DSD 2003: 451-454
	2002
c3		Jan Hlavicka, Petr Fiser: Minimization and Partitioning Method Reducing Input Sets. DELTA 2002: 434-436
	2001
c2		Petr Fiser, Jan Hlavicka: On the Use of Mutations in Boolean Minimization. DSD 2001: 300-309
c1		Jan Hlavicka, Petr Fiser: BOOM - A Heuristic Boolean Minimizer. ICCAD 2001: 439-442

Coauthor Index

1	Jiri Balcarek	[j3] [c20] [c19] [c16]
2	Jan Hlavicka	[j1] [c4] [c3] [c2] [c1]
3	Pavel Kubalík	[c11] [c7]
4	Hana Kubatova (Hana Kubátová)	[j2] [c11] [c9] [c8] [c7] [c6] [c5] [c4]
5	Igor Lemberski	[c17] [c15]
6	Pemysl Rucký	[c12]
7	Jan Schmidt	[j3] [c21] [c20] [c19] [c18] [c16] [c14]
8	Lukás Sekanina	[c18]
9	David Toman	[c13]
10	Irena Vanová	[c12]
11	Zdenek Vasícek	[c18]

Colors in the list of coauthors

Last update Sat May 25 01:34:37 2013 CET by the DBLP Team —

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