DBLP: Paulo F. Flores

	2013
j12		Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro: Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. IEEE Trans. VLSI Syst. 21(3): 498-511 (2013)
	2012
j11		Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro: High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. Integration 45(3): 294-306 (2012)
j10		Nuno Sebastião, Nuno Roma, Paulo F. Flores: Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase. Microprocessors and Microsystems - Embedded Hardware Design 36(2): 96-109 (2012)
j9		Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Optimization Algorithms for the Multiplierless Realization of Linear Transforms. ACM Trans. Design Autom. Electr. Syst. 17(1): 3 (2012)
j8		Nuno Sebastião, Nuno Roma, Paulo F. Flores: Integrated Hardware Architecture for Efficient Computation of the $n$-Best Bio-Sequence Local Alignments in Embedded Platforms. IEEE Trans. VLSI Syst. 20(7): 1262-1275 (2012)
c26		Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Design of low-complexity digital finite impulse response filters on FPGAs. DATE 2012: 1197-1202
c25		Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Multiple tunable constant multiplications: Algorithms and applications. ICCAD 2012: 473-479
	2011
j7		Cristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José Monteiro: Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. J. Low Power Electronics 7(2): 294-301 (2011)
j6		Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro: Finding the optimal tradeoff between area and delay in multiple constant multiplications. Microprocessors and Microsystems - Embedded Hardware Design 35(8): 729-741 (2011)
c24		Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Optimization of gate-level area in high throughput Multiple Constant Multiplications. ECCTD 2011: 588-591
c23		Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Efficient shift-adds design of digit-serial multiple constant multiplications. ACM Great Lakes Symposium on VLSI 2011: 61-66
c22		Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Design of low-power multiple constant multiplications using low-complexity minimum depth operations. ACM Great Lakes Symposium on VLSI 2011: 79-84
c21		Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. ISCAS 2011: 2737-2740
c20		Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: A hybrid algorithm for the optimization of area and delay in linear DSP transforms. VLSI-SoC 2011: 148-153
	2010
j5		Levent Aksoy, Ece Olcay Günes, Paulo F. Flores: Search algorithms for the multiple constant multiplications problem: Exact and approximate. Microprocessors and Microsystems - Embedded Hardware Design 34(5): 151-162 (2010)
c19		Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro: A new quaternary FPGA based on a voltage-mode multi-valued circuit. DATE 2010: 1797-1802
c18		Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. DSD 2010: 3-10
c17		Nuno Sebastião, Tiago Dias, Nuno Roma, Paulo F. Flores: Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase. HPCS 2010: 16-23
c16		Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro: Voltage-mode quaternary FPGAs: An evaluation of interconnections. ISCAS 2010: 869-872
c15		Cristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José C. Monteiro: An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. PATMOS 2010: 84-93
c14		Diego Jaccottet, Eduardo Costa, Levent Aksoy, Paulo F. Flores, José C. Monteiro: Design of low-complexity and high-speed digital Finite Impulse Response filters. VLSI-SoC 2010: 292-297
	2009
j4		Luís Gil, Paulo F. Flores, Luis Miguel Silveira: PMSat: a parallel version of MiniSAT. JSAT 6(1-3): 71-98 (2009)
j3		Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira: Generating realistic stimuli for accurate power grid analysis. ACM Trans. Design Autom. Electr. Syst. 14(3) (2009)
	2008
j2		Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro: Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1013-1026 (2008)
c13		Nuno Sebastião, Tiago Dias, Nuno Roma, Paulo F. Flores, Leonel Sousa: Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units. DSD 2008: 181-188
c12		Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro, Luis Miguel Silveira: Generating Worst-Case Stimuli for Accurate Power Grid Analysis. PATMOS 2008: 247-257
	2007
c11		Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José C. Monteiro: Optimization of Area in Digital FIR Filters using Gate-Level Metrics. DAC 2007: 420-423
c10		Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira: Generating Realistic Stimuli for Accurate Power Grid Analysis. ISVLSI 2007: 233-238
c9		Levent Aksoy, Ece Olcay Günes, Eduardo A. C. da Costa, Paulo F. Flores, José C. Monteiro: Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. SiPS 2007: 424-429
	2006
c8		Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro: Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. DAC 2006: 669-674
c7		Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro: Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. SBCCI 2006: 161-166
	2005
c6		Paulo F. Flores, José C. Monteiro, Eduardo A. C. da Costa: An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. ICCAD 2005: 13-16
	2001
j1		Paulo F. Flores, Horácio C. Neto, João P. Marques Silva: An exact solution to the minimum size test pattern problem. ACM Trans. Design Autom. Electr. Syst. 6(4): 629-644 (2001)
	1999
c5		Paulo F. Flores, Horácio C. Neto, João P. Marques Silva: On Applying Set Covering Models to Test Set Compaction. Great Lakes Symposium on VLSI 1999: 8-11
c4		Paulo F. Flores, Horácio C. Neto, K. Chakrabarty, João P. Marques Silva: Test pattern generation for width compression in BIST. ISCAS (1) 1999: 114-118
c3		Paulo F. Flores, José C. Costa, Horácio C. Neto, José C. Monteiro, João P. Marques Silva: Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. VLSI Design 1999: 37-41
	1998
c2		Paulo F. Flores, Horácio C. Neto, João P. Marques Silva: An exact solution to the minimum size test pattern problem. ICCD 1998: 510-515
	1997
c1		Vasco M. Manquinho, Paulo F. Flores, João P. Marques Silva, Arlindo L. Oliveira: Prime Implicant Computation Using Satisfiability Algorithms. ICTAI 1997: 232-239

2013

j12

Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro: Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. IEEE Trans. VLSI Syst. 21(3): 498-511 (2013)

2012

j11

Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro: High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. Integration 45(3): 294-306 (2012)

j10

Nuno Sebastião, Nuno Roma, Paulo F. Flores: Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase. Microprocessors and Microsystems - Embedded Hardware Design 36(2): 96-109 (2012)

Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Optimization Algorithms for the Multiplierless Realization of Linear Transforms. ACM Trans. Design Autom. Electr. Syst. 17(1): 3 (2012)

Nuno Sebastião, Nuno Roma, Paulo F. Flores: Integrated Hardware Architecture for Efficient Computation of the $n$-Best Bio-Sequence Local Alignments in Embedded Platforms. IEEE Trans. VLSI Syst. 20(7): 1262-1275 (2012)

c26

Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Design of low-complexity digital finite impulse response filters on FPGAs. DATE 2012: 1197-1202

c25

Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Multiple tunable constant multiplications: Algorithms and applications. ICCAD 2012: 473-479

2011

Cristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José Monteiro: Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. J. Low Power Electronics 7(2): 294-301 (2011)

Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro: Finding the optimal tradeoff between area and delay in multiple constant multiplications. Microprocessors and Microsystems - Embedded Hardware Design 35(8): 729-741 (2011)

c24

Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Optimization of gate-level area in high throughput Multiple Constant Multiplications. ECCTD 2011: 588-591

c23

Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Efficient shift-adds design of digit-serial multiple constant multiplications. ACM Great Lakes Symposium on VLSI 2011: 61-66

c22

Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Design of low-power multiple constant multiplications using low-complexity minimum depth operations. ACM Great Lakes Symposium on VLSI 2011: 79-84

c21

Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. ISCAS 2011: 2737-2740

c20

Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: A hybrid algorithm for the optimization of area and delay in linear DSP transforms. VLSI-SoC 2011: 148-153

2010

Levent Aksoy, Ece Olcay Günes, Paulo F. Flores: Search algorithms for the multiple constant multiplications problem: Exact and approximate. Microprocessors and Microsystems - Embedded Hardware Design 34(5): 151-162 (2010)

c19

Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro: A new quaternary FPGA based on a voltage-mode multi-valued circuit. DATE 2010: 1797-1802

c18

Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro: Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. DSD 2010: 3-10

c17

Nuno Sebastião, Tiago Dias, Nuno Roma, Paulo F. Flores: Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase. HPCS 2010: 16-23

c16

Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro: Voltage-mode quaternary FPGAs: An evaluation of interconnections. ISCAS 2010: 869-872

c15

Cristiano Lazzari, Jorge Fernandes, Paulo F. Flores, José C. Monteiro: An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. PATMOS 2010: 84-93

c14

Diego Jaccottet, Eduardo Costa, Levent Aksoy, Paulo F. Flores, José C. Monteiro: Design of low-complexity and high-speed digital Finite Impulse Response filters. VLSI-SoC 2010: 292-297

2009

Luís Gil, Paulo F. Flores, Luis Miguel Silveira: PMSat: a parallel version of MiniSAT. JSAT 6(1-3): 71-98 (2009)

Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira: Generating realistic stimuli for accurate power grid analysis. ACM Trans. Design Autom. Electr. Syst. 14(3) (2009)

2008

Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro: Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1013-1026 (2008)

c13

Nuno Sebastião, Tiago Dias, Nuno Roma, Paulo F. Flores, Leonel Sousa: Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units. DSD 2008: 181-188

c12

Pedro Marques Morgado, Paulo F. Flores, José C. Monteiro, Luis Miguel Silveira: Generating Worst-Case Stimuli for Accurate Power Grid Analysis. PATMOS 2008: 247-257

2007

c11

Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José C. Monteiro: Optimization of Area in Digital FIR Filters using Gate-Level Metrics. DAC 2007: 420-423

c10

Pedro Marques Morgado, Paulo F. Flores, L. Miguel Silveira: Generating Realistic Stimuli for Accurate Power Grid Analysis. ISVLSI 2007: 233-238

Levent Aksoy, Ece Olcay Günes, Eduardo A. C. da Costa, Paulo F. Flores, José C. Monteiro: Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. SiPS 2007: 424-429

2006

Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro: Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. DAC 2006: 669-674

Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro: Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. SBCCI 2006: 161-166

2005

Paulo F. Flores, José C. Monteiro, Eduardo A. C. da Costa: An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. ICCAD 2005: 13-16

2001

Paulo F. Flores, Horácio C. Neto, João P. Marques Silva: An exact solution to the minimum size test pattern problem. ACM Trans. Design Autom. Electr. Syst. 6(4): 629-644 (2001)

1999

Paulo F. Flores, Horácio C. Neto, João P. Marques Silva: On Applying Set Covering Models to Test Set Compaction. Great Lakes Symposium on VLSI 1999: 8-11

Paulo F. Flores, Horácio C. Neto, K. Chakrabarty, João P. Marques Silva: Test pattern generation for width compression in BIST. ISCAS (1) 1999: 114-118

Paulo F. Flores, José C. Costa, Horácio C. Neto, José C. Monteiro, João P. Marques Silva: Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. VLSI Design 1999: 37-41

1998

Paulo F. Flores, Horácio C. Neto, João P. Marques Silva: An exact solution to the minimum size test pattern problem. ICCD 1998: 510-515

1997

Vasco M. Manquinho, Paulo F. Flores, João P. Marques Silva, Arlindo L. Oliveira: Prime Implicant Computation Using Satisfiability Algorithms. ICTAI 1997: 232-239

1	Levent Aksoy	[j12] [j11] [j9] [c26] [c25] [j6] [c24] [c23] [c22] [c21] [c20] [j5] [c18] [c14] [j2] [c11] [c9] [c8]
2	Luigi Carro	[c19] [c16]
3	K. Chakrabarty	[c4]
4	Eduardo Costa	[j12] [j11] [j9] [c26] [c25] [j6] [c24] [c23] [c22] [c21] [c20] [c18] [c14]
5	Eduardo A. C. da Costa	[j2] [c11] [c9] [c8] [c7] [c6]
6	José C. Costa	[c3]
7	Tiago Dias	[c17] [c13]
8	Jorge Fernandes	[j7] [c15]
9	Luís Gil	[j4]
10	Ece Olcay Günes	[j5] [c9]
11	Diego Jaccottet	[c14]
12	Cristiano Lazzari	[j12] [j11] [j7] [c23] [c21] [c19] [c16] [c15]
13	Vasco M. Manquinho	[c1]
14	José C. Monteiro (José Monteiro)	[j12] [j11] [j9] [c26] [c25] [j7] [j6] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c16] [c15] [c14] [j2] [c12] [c11] [c9] [c8] [c7] [c6] [c3]
15	Pedro Marques Morgado	[j3] [c12] [c10]
16	Horácio C. Neto	[j1] [c5] [c4] [c3] [c2]
17	Arlindo L. Oliveira	[c1]
18	Nuno Roma (Nuno Filipe Valentim Roma)	[j10] [j8] [c17] [c13]
19	Nuno Sebastião	[j10] [j8] [c17] [c13]
20	João P. Marques Silva (João Marques-Silva)	[j1] [c5] [c4] [c3] [c2] [c1]
21	Luis Miguel Silveira (L. Miguel Silveira)	[j4] [j3] [c12] [c10]
22	Leonel Sousa (Leonel Augusto Sousa)	[c13]

Paulo F. Flores

Coauthor Index