Laurent Fournier

Laurent Fournier: Économie des biens immatériels - Economics of Intangible Goods. CoRR abs/1210.4014 (2012)

Dorit Baras, Shai Fine, Laurent Fournier, Dan Geiger, Avi Ziv: Automatic boosting of cross-product coverage using Bayesian networks. STTT 13(3): 247-261 (2011)

Laurent Fournier, Avi Ziv, Ekaterina Kutsy, Ofer Strichman: A probabilistic analysis of coverage methods. ACM Trans. Design Autom. Electr. Syst. 16(4): 38 (2011)

Ariel Birnbaum, Laurent Fournier, Steven Mittermaier, Avi Ziv: Reverse Coverage Analysis. Haifa Verification Conference 2011: 190-202

Shai Fine, Laurent Fournier, Avi Ziv: Using Bayesian networks and virtual coverage to hit hard-to-reach events. STTT 11(4): 291-305 (2009)

Dorit Baras, Laurent Fournier, Avi Ziv: Automatic Boosting of Cross-Product Coverage Using Bayesian Networks. Haifa Verification Conference 2008: 53-67

Allon Adir, Sigal Asaf, Laurent Fournier, Itai Jaeger, Ofer Peled: A Framework for the Validation of Processor Architecture Compliance. DAC 2007: 902-905

Laurent Fournier, Avi Ziv: Using Virtual Coverage to Hit Hard-To-Reach Events. Haifa Verification Conference 2007: 104-119

Hezi Azatchi, Laurent Fournier, Eitan Marcus, Shmuel Ur, Avi Ziv, Keren Zohar: Advanced Analysis Techniques for Cross-Product Coverage. IEEE Trans. Computers 55(11): 1367-1379 (2006)

Allon Adir, Laurent Fournier, Yoav Katz, Anatoly Koyfman: DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms. HLDVT 2006: 102-110

Hezi Azatchi, Laurent Fournier, Avi Ziv, Keren Zohar: Advanced analysis techniques for cross-product coverage. HLDVT 2005: 229-236

Allon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv: Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification. IEEE Design & Test of Computers 21(2): 84-93 (2004)

Eyal Bin, Laurent Fournier: Micro-Architecture Verification for Microprocessors. MTV 2004: 112-113

Avi Ziv, Laurent Fournier: Solving the generalized mask constraint for test generation of binary floating point add operation. Theor. Comput. Sci. 291(2): 183-201 (2003)

Merav Aharoni, Sigal Asaf, Laurent Fournier, Anatoly Koyfman, Raviv Nagel: FPgen - a test generation framework for datapath floating-point verification. HLDVT 2003: 17-22

Laurent Fournier, Anatoly Koyfman, Moshe Levinger: Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture. DAC 1999: 189-194

Laurent Fournier, Yaron Arbetman, Moshe Levinger: Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family. DATE 1999: 434-441