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 | 2004 | |
|---|---|---|
| j3 |      | Trevor W. Fox, Alex Carreira: A Digital Signal Processing Method for Gene Prediction with Improved Noise Suppression. EURASIP J. Adv. Sig. Proc. 2004(1): 108-114 (2004) |
| 2003 | ||
| j2 | | Trevor W. Fox, Laurence E. Turner: Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations. EURASIP J. Adv. Sig. Proc. 2003(6): 543-554 (2003) |
| j1 | | Alex Carreira, Trevor W. Fox, Laurence E. Turner: A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs. EURASIP J. Adv. Sig. Proc. 2003(6): 555-564 (2003) |
| c7 | | |
| c6 | | Trevor W. Fox, Alex Carreira, Laurence E. Turner: The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks. IWSOC 2003: 53-58 |
| 2002 | ||
| c5 | | Alex Carreira, Trevor W. Fox, Laurence E. Turner: A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM. FPL 2002: 222-231 |
| c4 | | Trevor W. Fox, Laurence E. Turner: Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. FPL 2002: 492-502 |
| c3 | | Alex Carreira, Trevor W. Fox, Laurence E. Turner: A method of implementing bit-serial LDI ladder filters in FPGAs using JBits. FPT 2002: 433-436 |
| c2 | | Trevor W. Fox, Laurence E. Turner: Low coefficient complexity approximations of the one dimensional discrete cosine transform. ISCAS (1) 2002: 285-288 |
| 2001 | ||
| c1 | | Trevor W. Fox, Laurence E. Turner: The design of peak constrained least squares FIR filters with low complexity finite precision coefficients. ISCAS (2) 2001: 605-608 |
| 1 | Alex Carreira | |
| 2 | Laurence E. Turner |
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