Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Joshua Friedrich
2010 – today
- 2012
[c9]Joshua Friedrich, Jinuk Luke Shin: Session 3 overview: Processors: High performance digital subcommittee. ISSCC 2012: 54-55
[c8]Stephen Kosonocky, Vladimir Stojanovic, Kees van Berkel, Ming-Yang Chao, Tobias Knoll, Joshua Friedrich: Power/performance optimization of many-core processor SoCs. ISSCC 2012: 508-509
[c7]Ichiro Fujimori, SeongHwan Cho, Joshua Friedrich, John Stonick: Optical PCB interconnects, Niche or mainstream? ISSCC 2012: 516- 2011
[j3]Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Buehler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez: Design methodology for the IBM POWER7 microprocessor. IBM Journal of Research and Development 55(3): 9 (2011)
[j2]Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban: POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. J. Solid-State Circuits 46(1): 145-161 (2011)- 2010
[c6]Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, R. Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban: The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor. ISSCC 2010: 102-103
[c5]James D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski: POWER7TM local clocking and clocked storage elements. ISSCC 2010: 178-179
2000 – 2009
- 2009
[c4]Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich: The opportunity cost of low power design: a case study in circuit tuning. ISLPED 2009: 133-138- 2008
[c3]Robert L. Franch, Phillip Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, G. Salem: On-chip Timing Uncertainty Measurements on IBM Microprocessors. ITC 2008: 1-7- 2007
[j1]Brian W. Curran, Eric Fluhr, Jose Paredes, Leon J. Sigal, Joshua Friedrich, Yiu-Hing Chan, Charlie Hwang: Power-constrained high-frequency circuits for the IBM POWER6 microprocessor. IBM Journal of Research and Development 51(6): 715-732 (2007)
[c2]Robert L. Franch, Phillip Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, G. Salem: On-chip timing uncertainty measurements on IBM microprocessors. ITC 2007: 1-7- 2004
[c1]Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson: Design and implementation of the POWER5 microprocessor. DAC 2004: 670-672
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2012-12-19 21:34 CET by the dblp team



