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Hiromu Fujioka
2000 – 2009
- 2007
[j8]Koji Nakamae, Masaki Chikahisa, Hiromu Fujioka: Estimation of electron probe profile from SEM image through wavelet multiresolution analysis for inline SEM inspection. Image Vision Comput. 25(7): 1117-1123 (2007)- 2003
- [j7]Katsuyoshi Miura, Tomoyuki Kobatake, Koji Nakamae, Hiromu Fujioka: A low energy FIB processing, repair, and test system. Microelectronics Reliability 43(9-11): 1627-1631 (2003)
- [c5]Youhei Zenda, Koji Nakamae, Hiromu Fujioka: Cost Optimum Embedded DRAM Design by Yield Analysis. MTDT 2003: 20-
- 2002
- [j6]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka: CAD navigation system, for backside waveform probing of CMOS devices. Microelectronics Reliability 42(9-11): 1679-1684 (2002)
- 2001
- [j5]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka: Development of an EB/FIB Integrated Test System. Microelectronics Reliability 41(9-10): 1489-1494 (2001)
- 2000
- [j4]Koji Nakamae, Takashi Ishimura, Hiromu Fujioka: EB tester fault localization algorithm for combinational circuits by utilizing fault simulation and test pattern sequence for EB tester. Systems and Computers in Japan 31(8): 41-48 (2000)
1990 – 1999
- 1999
- [c4]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka: Intelligent EB Test System for Automatic VLSI Fault Tracing. Asian Test Symposium 1999: 335-341
- 1998
- [j3]Koji Nakamae, Shinji Yokoyama, Atsushi Onishi, Hiromu Fujioka: Knowledge-based circuit recognition from standard-cell design CMOS VLSI optical microscope images. Systems and Computers in Japan 29(4): 70-78 (1998)
- 1997
- [j2]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka: Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. J. Electronic Testing 10(3): 255-269 (1997)
- [c3]Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka: Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system. ASP-DAC 1997: 329-332
- [c2]Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka: Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data. Asian Test Symposium 1997: 162-167
- 1996
- [j1]Koji Nakamae, Homare Sakamoto, Hiromu Fujioka: How ATE Planning Affects LSI Manufacturing Cost. IEEE Design & Test of Computers 13(4): 66-73 (1996)
- [c1]Hiromu Fujioka, Koji Nakamae, Akio Higashi: Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost. ITC 1996: 793-799
Coauthor Index
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last updated on 2013-05-01 23:01 CEST by the dblp team