Stephen B. Furber

Alexander D. Rast, Javier Navaridas, Xin Jin, Francesco Galluppi, Luis A. Plana, José Miguel-Alonso, Cameron Patterson, Mikel Luján, Steve Furber: Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System. International Journal of Parallel Programming 40(6): 553-582 (2012)

Cameron Patterson, Jim D. Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve Furber: Scalable communications for a million-core neural processing architecture. J. Parallel Distrib. Comput. 72(11): 1507-1520 (2012)

Sergio Davies, Francesco Galluppi, Alexander D. Rast, Stephen B. Furber: A forecast-based STDP rule suitable for neuromorphic implementation. Neural Networks 32: 3-14 (2012)

Andrew Mundy, Terrence S. T. Mak, Alex Yakovlev, Simon Davidson, Steve Furber: Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication. ACSD 2012: 62-71

Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana: An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. ASYNC 2012: 49-56

Francesco Galluppi, Sergio Davies, Alexander D. Rast, Thomas Sharp, Luis A. Plana, Steve Furber: A hierachical configuration system for a massively parallel neural hardware platform. Conf. Computing Frontiers 2012: 183-192

Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve Furber: SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. CICC 2012: 1-4

Cameron Patterson, Thomas Preston, Francesco Galluppi, Steve Furber: Managing a Massively-Parallel Resource-Constrained Computing Architecture. DSD 2012: 723-726

Javier Navaridas, Mikel Luján, Luis A. Plana, José Miguel-Alonso, Stephen B. Furber: Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System. HPCC-ICESS 2012: 1-8

Francesco Galluppi, Kevin Brohan, Simon Davidson, Teresa Serrano-Gotarredona, José Antonio Pérez-Carrasco, Bernabé Linares-Barranco, Steve Furber: A Real-Time, Event-Driven Neuromorphic System for Goal-Directed Attentional Selection. ICONIP (2) 2012: 226-233

Sergio Davies, Javier Navaridas, Francesco Galluppi, Steve Furber: Population-based routing in the SpiNNaker neuromorphic architecture. IJCNN 2012: 1-8

Francesco Galluppi, Sergio Davies, Steve Furber, Terry Stewart, Chris Eliasmith: Real time on-chip implementation of dynamical systems with spiking neurons. IJCNN 2012: 1-8

Cameron Patterson, Francesco Galluppi, Alexander D. Rast, Steve Furber: Visualising large-scale neural network models in real-time. IJCNN 2012: 1-8

Alexander D. Rast, Luis A. Plana, Stephen R. Welbourne, Stephen B. Furber: Event-driven MLP implementation on neuromimetic hardware. IJCNN 2012: 1-8

Luis A. Plana, David M. Clark, Simon Davidson, Steve Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge: SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. JETC 7(4): 17 (2011)

Alexander D. Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Cameron Patterson, Thomas Sharp, David R. Lester, Steve Furber: Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware. Neural Networks 24(9): 961-978 (2011)

Mukaram M. Khan, Alexander D. Rast, Javier Navaridas, X. Jin, Luis A. Plana, Mikel Luján, Steve Temple, Cameron Patterson, D. Richards, John V. Woods, José Miguel-Alonso, Stephen B. Furber: Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric. Parallel Computing 37(8): 392-409 (2011)

Martin Grymel, Steve Furber: A Novel Programmable Parallel CRC Circuit. IEEE Trans. VLSI Syst. 19(10): 1898-1902 (2011)

Steve Furber: Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform. ARC 2011: 2

Sergio Davies, Alexander D. Rast, Francesco Galluppi, Steve Furber: Maintaining real-time synchrony on SpiNNaker. Conf. Computing Frontiers 2011: 15

Stephen B. Furber: Biologically-inspired massively-parallel architectures - Computing beyond a million processors. DATE 2011: 1

Michael Merrett, Plamen Asenov, Yangang Wang, Mark Zwolinski, Dave Reid, Campbell Millar, Scott Roy, Zhenyu Liu, Stephen B. Furber, Asen Asenov: Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis. DATE 2011: 1537-1540

Thomas Sharp, Luis A. Plana, Francesco Galluppi, Steve Furber: Event-Driven Simulation of Arbitrary Spiking Neural Networks on SpiNNaker. ICONIP (3) 2011: 424-430

Francesco Galluppi, Steve Furber: Representing and decoding rank order codes using polychronization in a network of spiking neurons. IJCNN 2011: 943-950

Thomas Sharp, Cameron Patterson, Steve Furber: Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware. IJCNN 2011: 1099-1105

Sergio Davies, Alexander D. Rast, Francesco Galluppi, Steve Furber: A forecast-based biologically-plausible STDP learning rule. IJCNN 2011: 1810-1817

Alexander D. Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Thomas Sharp, Steve Furber: An event-driven model for the SpiNNaker virtual synaptic channel. IJCNN 2011: 1967-1974

David R. Lester, Steve Furber: SpiNNaker: Distributed Computer Engineering for Neuromorphics. WIRN 2011: 324-331

Jian Wu, Steve Furber: A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture. Comput. J. 53(3): 280-288 (2010)

Xin Jin, Mikel Luján, Luis A. Plana, Sergio Davies, Steve Temple, Steve Furber: Modeling Spiking Neural Networks on SpiNNaker. Computing in Science and Engineering 12(5): 91-97 (2010)

Basabdatta Sen Bhattacharya, Stephen B. Furber: Biologically inspired means for rank-order encoding images: a quantitative analysis. IEEE Transactions on Neural Networks 21(7): 1087-1099 (2010)

Javier Navaridas, Luis A. Plana, José Miguel-Alonso, Mikel Luján, Stephen B. Furber: SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network. Conf. Computing Frontiers 2010: 11-20

Alexander D. Rast, Xin Jin, Francesco Galluppi, Luis A. Plana, Cameron Patterson, Stephen B. Furber: Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. Conf. Computing Frontiers 2010: 21-30

Andrew D. Brown, Steve Furber, Jeff S. Reeve, Peter R. Wilson, Mark Zwolinski, John E. Chad, Luis A. Plana, David R. Lester: A communication infrastructure for a million processor machine. Conf. Computing Frontiers 2010: 75-76

Xin Jin, Mikel Luján, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Steve Furber: Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker. Conf. Computing Frontiers 2010: 89-90

Francesco Galluppi, Alexander D. Rast, Sergio Davies, Steve Furber: A General-Purpose Model Translation System for a Universal Neural Chip. ICONIP (1) 2010: 58-65

Xin Jin, Francesco Galluppi, Cameron Patterson, Alexander D. Rast, Sergio Davies, Steve Temple, Steve Furber: Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system. IJCNN 2010: 1-8

Xin Jin, Alexander D. Rast, Francesco Galluppi, Sergio Davies, Steve Furber: Implementing spike-timing-dependent plasticity on SpiNNaker neuromorphic hardware. IJCNN 2010: 1-8

Alexander D. Rast, Francesco Galluppi, Xin Jin, Steve Furber: The Leaky Integrate-and-Fire neuron: A platform for synaptic model exploration on the SpiNNaker chip. IJCNN 2010: 1-8

Xin Jin, Mikel Luján, Muhammad Mukaram Khan, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Stephen B. Furber: Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware. ISPDC 2010: 9-16

Shufan Yang, Stephen B. Furber, Yebin Shi, Luis A. Plana: A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect. Fundam. Inform. 95(1): 53-72 (2009)

Stephen B. Furber, Andrew D. Brown: Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors. ACSD 2009: 3-12

Jim D. Garside, Stephen B. Furber, Steve Temple, Viv Woods: The Amulet chips: Architectural development for asynchronous microprocessors. ICECS 2009: 343-346

Xin Jin, Alexander D. Rast, Francesco Galluppi, Muhammad Mukaram Khan, Steve Furber: Implementing Learning on the SpiNNaker Universal Neural Chip Multiprocessor. ICONIP (1) 2009: 425-432

Javier Navaridas, Mikel Luján, José Miguel-Alonso, Luis A. Plana, Steve Furber: Understanding the interconnection network of SpiNNaker. ICS 2009: 286-295

Alexander D. Rast, Mukaram M. Khan, Xin Jin, Luis A. Plana, Steve Furber: A universal abstract-time platform for real-time neural networks. IJCNN 2009: 2611-2618

Alexander D. Rast, Stephen R. Welbourne, Xin Jin, Steve Furber: Optimal connectivity in hardware-targetted MLP networks. IJCNN 2009: 2619-2626

Basabdatta Sen Bhattacharya, Steve Furber: Evaluating rank-order code performance using a biologically-derived retinal model. IJCNN 2009: 2867-2874

Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steve Furber: Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric. ISPDC 2009: 54-61

Shufan Yang, Stephen B. Furber, Luis A. Plana: Adaptive admission control on the SpiNNaker MPSoC. SoCC 2009: 243-246

Steve Furber: The Future of Computer Technology and its Implications for the Computer Industry. Comput. J. 51(6): 735-740 (2008)

Shufan Yang, Steve Furber, Yebin Shi, Luis A. Plana: An admission control system for QoS provision on a best-effort GALS interconnect. ACSD 2008: 200-207

Andrew D. Brown, David R. Lester, Luis A. Plana, Steve Furber, Peter R. Wilson: SpiNNaker: The Design Automation Problem. ICONIP (2) 2008: 1049-1056

Alexander D. Rast, Xin Jin, Muhammad Mukaram Khan, Steve Furber: The Deferred Event Model for Hardware-Oriented Spiking Neural Networks. ICONIP (2) 2008: 1057-1064

Alexander D. Rast, Shufan Yang, Muhammad Mukaram Khan, Stephen B. Furber: Virtual synaptic interconnect using an asynchronous network-on-chip. IJCNN 2008: 2727-2734

Xin Jin, Stephen B. Furber, John V. Woods: Efficient modelling of spiking neural networks on a scalable chip multiprocessor. IJCNN 2008: 2812-2819

Muhammad Mukaram Khan, David R. Lester, Luis A. Plana, Alexander D. Rast, Xin Jin, Eustace Painkras, Stephen B. Furber: SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. IJCNN 2008: 2849-2856

Luis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu: An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. NOCS 2008: 215-216

Steve Furber, Steve Temple: Neural Systems Engineering. Computational Intelligence: A Compendium 2008: 763-796

Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang: A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Design & Test of Computers 24(5): 454-463 (2007)

Stephen B. Furber, G. Brown, Joy Bose, J. Mike Cumpstey, P. Marshall, Jonathan L. Shapiro: Sparse Distributed Memory Using Rank-Order Neural Codes. IEEE Transactions on Neural Networks 18(3): 648-659 (2007)

Jo C. Ebergen, Steve Furber, Arash Saifhashemi: Notes On Pulse Signaling. ASYNC 2007: 15-24

Steve Furber: Living with Failure: Lessons from Nature? European Test Symposium 2006: 4-8

Stephen B. Furber, Steve Temple, Andrew D. Brown: On-chip and inter-chip networks for modeling large-scale neural systems. ISCAS 2006

Yijun Liu, Steve Furber, Zhenkun Li: The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing. PATMOS 2006: 425-438

Joy Bose, Stephen B. Furber, Jonathan L. Shapiro: An associative memory for the on-line recognition and prediction of temporal sequences. CoRR abs/cs/0611020 (2006)

Joy Bose, Stephen B. Furber, Jonathan L. Shapiro: A Spiking Neural Sparse Distributed Memory Implementation for Learning and Predicting Temporal Sequences. ICANN (1) 2005: 115-120

Yijun Liu, Stephen B. Furber: A Low Power Embedded Dataflow Coprocessor. ISVLSI 2005: 246-247

Yijun Liu, Stephen B. Furber: The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. PATMOS 2005: 647-656

Joy Bose, Stephen B. Furber, Jonathan L. Shapiro: A System for Transmitting a Coherent Burst of Activity Through a Network of Spiking Neurons. WIRN/NAIS 2005: 44-48

Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple: Sparse distributed memory using N-of-M codes. Neural Networks 17(10): 1437-1451 (2004)

Alexandre Yakovlev, Stephen B. Furber, René Krenz, Alexandre V. Bystrov: Design and Analysis of a Self-Timed Duplex Communication System. IEEE Trans. Computers 53(7): 798-814 (2004)

W. J. Bainbridge, Luis A. Plana, Stephen B. Furber: The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. DATE 2004: 274-279

Yijun Liu, Stephen B. Furber: The design of a low power asynchronous multiplier. ISLPED 2004: 301-306

Yijun Liu, Stephen B. Furber: Minimizing the Power Consumption of an Asynchronous Multiplier. PATMOS 2004: 289-300

Tomaz Feliciian, Stephen B. Furber: An asynchronous on-chip network router with quality-of-service (QoS) support. SoCC 2004: 274-277

Steve Furber: Editorial. Microprocessors and Microsystems 27(9): 407-408 (2003)

Daranee Hormdee, Jim D. Garside, Stephen B. Furber: An asynchronous copy-back cache architecture. Microprocessors and Microsystems 27(10): 485-500 (2003)

T. Felicijan, Stephen B. Furber: An asynchronous ternary logic signaling system. IEEE Trans. VLSI Syst. 11(6): 1114-1119 (2003)

W. J. Bainbridge, W. B. Toms, David A. Edwards, Stephen B. Furber: Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. ASYNC 2003: 132-140

Z. C. Yu, Stephen B. Furber, Luis A. Plana: An Investigation into the Security of Self-Timed Circuits. ASYNC 2003: 206-215

Stephen B. Furber: Validating the AMULET Microprocessors. Comput. J. 45(1): 19-26 (2002)

John Bainbridge, Stephen B. Furber: Chain: A Delay-Insensitive Chip Area Interconnect. IEEE Micro 22(5): 16-23 (2002)

Daranee Hormdee, Jim D. Garside, Stephen B. Furber: An Asynchronous Victim Cache. DSD 2002: 4-11

Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple: Power Management in the Amulet Microprocessors. IEEE Design & Test of Computers 18(2): 42-52 (2001)

P. A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber: A Low-Power Self-Timed Viterbi Decoder. ASYNC 2001: 15-24

W. J. Bainbridge, Stephen B. Furber: Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. ASYNC 2001: 118-126

W. J. Bainbridge, Stephen B. Furber: MARBLE: an asynchronous on-chip macrocell bus. Microprocessors and Microsystems - Embedded Hardware Design 24(4): 213-222 (2000)

Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, John V. Woods, Jianwei Liu, O. Petli: AMULET3i - An Asynchronous System-on-Chip. ASYNC 2000: 162-175

Stephen B. Furber, David A. Edwards, Jim D. Garside: AMULET3: A 100 MIPS Asynchronous Embedded Processor. ICCD 2000: 329-334

Jim D. Garside, Stephen B. Furber, S.-H. Chung: AMULET3 Revealed. ASYNC 1999: 51-59

W. J. Bainbridge, Stephen B. Furber: Asynchronous Macrocell Interconnect using MARBLE. ASYNC 1998: 122-132

Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen: The Design of an Asynchronous VHDL Synthesizer. DATE 1998: 44-51

Philip Endecott, Stephen B. Furber: Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language. ESM 1998: 39-43

Stephen B. Furber, Jim D. Garside, D. A. Gilbert: AMULET3: a high-performance self-timed ARM microprocessor. ICCD 1998: 247-252

John V. Woods, P. Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple: AMULET1: A Asynchronous ARM Microprocessor. IEEE Trans. Computers 46(4): 385-398 (1997)

O. A. Petlin, Stephen B. Furber: Built-In Self-Testing of Micropipelines. ASYNC 1997: 22-29

Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver: AMULET2e: An Asynchronous Embedded Controller. ASYNC 1997: 290-

Stephen B. Furber, P. Day: Four-phase micropipeline latch control circuits. IEEE Trans. VLSI Syst. 4(2): 247-253 (1996)

Stephen B. Furber: The Return of Asynchronous Logic. ITC 1996: 938

O. A. Petlin, Stephen B. Furber: Scan testing of asynchronous sequential circuits. Great Lakes Symposium on VLSI 1995: 224-229

O. A. Petlin, Stephen B. Furber: Scan testing of micropipelines. VTS 1995: 296-303

Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, John V. Woods: AMULET1: A Micropipelined ARM. COMPCON 1994: 476-485

Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods: The Design and Evaluation of an Asynchronous Microprocessor. ICCD 1994: 217-220

Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, John V. Woods: A micropipelined ARM. VLSI 1993: 211-220

Stephen B. Furber, Martyn Edwards (Eds.): Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993. IFIP Transactions A-28, North-Holland 1993, isbn 0-444-81599-6

N. C. Paver, P. Day, Stephen B. Furber, Jim D. Garside, John V. Woods: Register Locking in an Asynchronous Microprocessor. ICCD 1992: 351-355