José Luís Almada Güntzel

José Luís Güntzel

	2013
c19		Vincius S. Livramento, Chrystian Guth, José Luís Güntzel, Marcelo O. Johann: Fast and efficient lagrangian relaxation-based discrete gate sizing. DATE 2013: 1855-1860
	2011
c18		Jucemar Monteiro, José Luís Güntzel, Luciano Volcan Agostini: A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design. ICECS 2011: 442-445
c17		Vincius S. Livramento, Bruno G. Moraes, Brunno Abner Machado, José Luís Güntzel: An energy-efficient 8×8 2-D DCT VLSI architecture for battery-powered portable devices. ISCAS 2011: 587-590
c16		Vincius S. Livramento, Bruno George de Moraes, Brunno Abner Machado, José Luís Almada Güntzel: An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms. SBCCI 2011: 149-154
c15		Daniel P. Volpato, Alexandre Keunecke Ignácio Mendonca, José Luís Almada Güntzel, Luiz Cláudio Villar dos Santos: Cache-tuning-aware scratchpad allocation from binaries. SBCCI 2011: 221-226
	2010
c14		Daniel P. Volpato, Alexandre K. I. Mendonça, Luiz C. V. dos Santos, José Luís Almada Güntzel: A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency. ISVLSI 2010: 127-132
	2009
c13		Alexandre K. I. Mendonça, Daniel P. Volpato, José Luís Almada Güntzel, Luiz C. V. dos Santos: Mapping Data and Code into Scratchpads from Relocatable Binaries. ISVLSI 2009: 157-162
	2007
c12		Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel: RIC Fast Adder and its Set Tolerant Implementation in FPGAs. FPL 2007: 638-641
	2006
c11		Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Leandro Rosa, José Luís Güntzel, Ivan Saraiva Silva: High throughput architecture for H.264/AVC forward transforms block. ACM Great Lakes Symposium on VLSI 2006: 320-323
c10		Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, José Luís Güntzel, Ivan Saraiva Silva, Sergio Bampi: High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard. ISCAS 2006
c9		Daniel Lima Ferrão, Ricardo Reis, José Luís Almada Güntzel: Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. PATMOS 2006: 301-310
	2005
c8		Cristiano Santos, Daniel Lima Ferrão, Ricardo Reis, José Luís Güntzel: Incremental timing optimization for automatic layout generation. ISCAS (4) 2005: 3567-3570
	2004
c7		Ricardo Reis, Fernanda Lima Kastensmidt, José Luís Almada Güntzel: Physical design methodologies for performance predictability and manufacturability. Conf. Computing Frontiers 2004: 390-397
c6		Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis: A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. PATMOS 2004: 732-741
	2003
c5		David Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán: Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510
c4		Daniel Lima Ferrão, Gustavo Wilke, Ricardo Augusto da Luz Reis, José Luís Almada Güntzel: Improving Critical Path Identification in Functional Timing Analysis. SBCCI 2003: 297-302
c3		Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel: A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. SBCCI 2003: 303-
c2		Cristiano Lazzari, Cristiano Viana Domingues, José Luís Almada Güntzel, Ricardo Augusto da Luz Reis: A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. VLSI-SOC 2003: 193-197
	2001
j1		José Luís Almada Güntzel, Ricardo Augusto da Luz Reis: Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas. RITA 8(1): 111-142 (2001)
	1999
c1		Fernanda Lima, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Augusto da Luz Reis: Designing a Mask Programmable Matrix for Sequential Circuits. VLSI 1999: 439-446

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