Tomasz Garbolino

Gregor Papa, Tomasz Garbolino: Optimal on-line built-in self-test structure for system-reliability improvement. IEEE Congress on Evolutionary Computation 2011: 222-229

Tomasz Garbolino, Gregor Papa: Genetic algorithm for test pattern generator design - Automatic evolution of circuits. Appl. Intell. 32(2): 193-204 (2010)

Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka: How to reduce size of a signature-based diagnostic dictionary used for testing of connections. DDECS 2010: 201-204

Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka: Effective BIST for crosstalk faults in interconnects. DDECS 2009: 164-169

Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec: Interconnect Faults Identification and Localization Using Modified Ring LFSRs. DDECS 2008: 247-250

Gregor Papa, Tomasz Garbolino, Franc Novak: Deterministic Test Pattern Generator Design. EvoWorkshops 2008: 204-213

Tomasz Garbolino, Gregor Papa: Test Pattern Generator Design Optimization Based on Genetic Algorithm. IEA/AIE 2008: 580-589

Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka: Avoiding Crosstalk Influence on Interconnect Delay Fault Testing. DDECS 2007: 149-152

Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino (Eds.): Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007. IEEE Computer Society 2007, isbn 1-4244-1161-0

Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka: Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor. DDECS 2006: 230-231

Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka: Test-per-Clock Detection, Localization and Identification of Interconnect Faults. European Test Symposium 2006: 233-238

Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa: Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. J. Electronic Testing 20(1): 109-122 (2004)

Tomasz Garbolino, Andrzej Hlawiczka: Efficient test pattern generators based on specific cellular automata structures. Microelectronics Reliability 42(6): 975-983 (2002)

Tomasz Garbolino, Andrzej Hlawiczka: A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits. EDCC 1999: 321-338