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Jim D. Garside
2010 – today
- 2012
[j8]Cameron Patterson, Jim D. Garside, Eustace Painkras, Steve Temple, Luis A. Plana, Javier Navaridas, Thomas Sharp, Steve Furber: Scalable communications for a million-core neural processing architecture. J. Parallel Distrib. Comput. 72(11): 1507-1520 (2012)- [c31]Geoffrey Ndu, Jim D. Garside: Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration. ARC 2012: 114-125
- [c30]Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana: An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. ASYNC 2012: 49-56
- [c29]Eustace Painkras, Luis A. Plana, Jim D. Garside, Steve Temple, Simon Davidson, Jeffrey Pepper, David M. Clark, Cameron Patterson, Steve Furber: SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation. CICC 2012: 1-4
- [c28]Wei Song, Doug Edwards, Jim D. Garside, William J. Bainbridge: Area efficient asynchronous SDM routers using 2-stage Clos switches. DATE 2012: 1495-1500
- 2011
- [j7]Luis A. Plana, David M. Clark, Simon Davidson, Steve Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge: SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. JETC 7(4): 17 (2011)
2000 – 2009
- 2009
- [c27]Jim D. Garside, Stephen B. Furber, Steve Temple, Viv Woods: The Amulet chips: Architectural development for asynchronous microprocessors. ICECS 2009: 343-346
- 2008
- [c26]Konstantinos Nikas, Matthew Horsnell, Jim D. Garside: An adaptive bloom filter cache partitioning scheme for multicore architectures. ICSAMOS 2008: 25-32
- 2007
- [c25]A. Robinson, Jim D. Garside: Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. ACM Great Lakes Symposium on VLSI 2007: 138-143
- 2005
- [c24]Aristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou: A Low-Power Processor Architecture Optimized forWireless Devices. ASAP 2005: 185-190
- [c23]C. Brej, Jim D. Garside: A Quasi-Delay-Insensitive Method to Overcome Transistor Variation. VLSI Design 2005: 368-373
- 2004
- [j6]Aristides Efthymiou, Jim D. Garside: A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Trans. VLSI Syst. 12(3): 325-329 (2004)
- [c22]Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury: An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ASYNC 2004: 207-215
- 2003
- [j5]Luis A. Plana, P. A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu: SPA - a secure Amulet core for smartcard applications. Microprocessors and Microsystems 27(9): 431-446 (2003)
- [j4]Daranee Hormdee, Jim D. Garside, Stephen B. Furber: An asynchronous copy-back cache architecture. Microprocessors and Microsystems 27(10): 485-500 (2003)
- [c21]Aristides Efthymiou, Jim D. Garside: Adaptive Pipeline Structures fo Speculation Control. ASYNC 2003: 46-55
- 2002
- [c20]W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, P. A. Riocreux, Luis A. Plana: SPA - A Synthesisable Amulet Core for Smartcard pplications. ASYNC 2002: 201-210
- [c19]
- [c18]Aristides Efthymiou, Jim D. Garside: Adaptive Pipeline Depth Control for Processor Power-Management. ICCD 2002: 454-457
- [c17]Aristides Efthymiou, Jim D. Garside: An adaptive serial-parallel CAM architecture for low-power cache blocks. ISLPED 2002: 136-141
- [c16]Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside: Logic Design of Asynchronous Circuits (Tutorial Abstract). VLSI Design 2002: 26-
- 2001
- [j3]Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple: Power Management in the Amulet Microprocessors. IEEE Design & Test of Computers 18(2): 42-52 (2001)
- [c15]David W. Lloyd, Jim D. Garside: A Practical Comparison of Asynchronous Design Styles. ASYNC 2001: 36-45
- [c14]
- 2000
- [c13]Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, John V. Woods, Jianwei Liu, O. Petli: AMULET3i - An Asynchronous System-on-Chip. ASYNC 2000: 162-175
- [c12]Stephen B. Furber, David A. Edwards, Jim D. Garside: AMULET3: A 100 MIPS Asynchronous Embedded Processor. ICCD 2000: 329-334
1990 – 1999
- 1999
- [c11]Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury: Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. ASYNC 1999: 27-35
- [c10]
- [c9]David W. Lloyd, Jim D. Garside, D. A. Gilbert: Memory Faults in Asynchronous Microprocessors. ASYNC 1999: 71-
- 1998
- [j2]Stephen B. Furber, Jim D. Garside, Steve Temple, Paul Day, Nigel C. Paver: Asynchronous Embedded Control. Integrated Computer-Aided Engineering 5(1): 57-68 (1998)
- [c8]Stephen B. Furber, Jim D. Garside, D. A. Gilbert: AMULET3: a high-performance self-timed ARM microprocessor. ICCD 1998: 247-252
- 1997
- [j1]John V. Woods, Paul Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple: AMULET1: A Asynchronous ARM Microprocessor. IEEE Trans. Computers 46(4): 385-398 (1997)
- [c7]D. A. Gilbert, Jim D. Garside: A Result Forwarding Mechanism for Asynchronous Pipelined Systems. ASYNC 1997: 2-11
- [c6]Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, Paul Day, N. C. Paver: AMULET2e: An Asynchronous Embedded Controller. ASYNC 1997: 290-
- 1994
- [c5]Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, John V. Woods: AMULET1: A Micropipelined ARM. COMPCON 1994: 476-485
- [c4]Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods: The Design and Evaluation of an Asynchronous Microprocessor. ICCD 1994: 217-220
- 1993
- [c3]Jim D. Garside: A CMOS VLSI Implementation of an Asynchronous ALU. Asynchronous Design Methodologies 1993: 181-192
- [c2]Stephen B. Furber, Paul Day, Jim D. Garside, N. C. Paver, John V. Woods: A micropipelined ARM. VLSI 1993: 211-220
- 1992
- [c1]N. C. Paver, Paul Day, Stephen B. Furber, Jim D. Garside, John V. Woods: Register Locking in an Asynchronous Microprocessor. ICCD 1992: 351-355
Coauthor Index
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last updated on 2013-06-13 23:35 CEST by the dblp team