Ran Ginosar

Salomon Beer, Ran Ginosar, Jerome Cox, Tom Chaney, David M. Zar: Metastability challenges for 65nm and beyond: simulation and measurements. DATE 2013: 1297-1302

Itai Avron, Ran Ginosar: Performance of a Hardware Scheduler for Many-core Architecture. HPCC-ICESS 2012: 151-160

Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Energy metrics for power efficient crosslink and mesh topologies. ISCAS 2012: 1656-1659

Salomon Beer, Ran Ginosar: An Extended Metastability Simulation Method for Synchronizer Characterization. PATMOS 2012: 42-51

Eyal-Itzhak Nave, Ran Ginosar: TCP Window Based DVFS for Low Power Network Controller SoC. PATMOS 2012: 83-92

Ran Ginosar: Metastability and Synchronizers: A Tutorial. IEEE Design & Test of Computers 28(5): 23-35 (2011)

Dmitri Vainbrand, Ran Ginosar: Scalable network-on-chip architecture for configurable neural networks. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 152-166 (2011)

Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny: An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. ISCAS 2011: 2593-2596

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. VLSI Syst. 18(5): 689-696 (2010)

Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar: Asynchronous Current Mode Serial Communication. IEEE Trans. VLSI Syst. 18(7): 1107-1117 (2010)

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. VLSI Syst. 18(8): 1262 (2010)

Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny: The Devolution of Synchronizers. ASYNC 2010: 94-103

Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI 2010: 15-20

Dmitri Vainbrand, Ran Ginosar: Network-on-Chip Architectures for Neural Networks. NOCS 2010: 135-144

Amit Berman, Ran Ginosar, Idit Keidar: Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip. VLSI-SoC 2010: 37-42

Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny: QNoC asynchronous router. Integration 42(2): 103-115 (2009)

Rostislav (Reuven) Dobkin, Ran Ginosar: Two-phase synchronization with sub-cycle latency. Integration 42(3): 367-375 (2009)

Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI 2009: 285-290

Asaf Baron, Ran Ginosar, Isaac Keslassy: The Capacity Allocation Paradox. INFOCOM 2009: 1359-1367

Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser: Multiple clock and voltage domains for chip multi processors. MICRO 2009: 459-468

A. Elyada, Ran Ginosar, Uri C. Weiser: Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. IEEE Trans. VLSI Syst. 16(9): 1243-1248 (2008)

Rostislav (Reuven) Dobkin, Ran Ginosar: Fast Universal Synchronizers. PATMOS 2008: 199-208

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Timing optimization in logic with interconnect. SLIP 2008: 19-26

Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar: Parallel vs. serial on-chip communication. SLIP 2008: 43-50

Yevgeny Perelman, Ran Ginosar: An Integrated System for Multichannel Neuronal Recording With Spike/LFP Separation, Integrated A/D Conversion and Threshold Detection. IEEE Trans. Biomed. Engineering 54(1): 130-137 (2007)

Rami Rom, Jacob Erel, Michael Glikson, Randy A. Lieberman, Kobi Rosenblum, Ofer Binah, Ran Ginosar, David L. Hayes: Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme. IEEE Transactions on Neural Networks 18(2): 542-550 (2007)

Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design 2007 (2007)

Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny: High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC 2007: 3-14

Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Routing table minimization for irregular mesh NoCs. DATE 2007: 942-947

Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny: The Power of Priority: NoC Based Distributed Cache Coherency. NOCS 2007: 117-126

Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Access Regulation to Hot-Modules in Wormhole NoCs. NOCS 2007: 137-148

Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon: QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. NOCS 2007: 218

Uri Frank, Tsachy Kapschitz, Ran Ginosar: A predictive synchronizer for periodic clock domains. Formal Methods in System Design 28(2): 171-186 (2006)

Ilya Obridko, Ran Ginosar: Minimal Energy Asynchronous Dynamic Adders. IEEE Trans. VLSI Syst. 14(9): 1043-1047 (2006)

Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou: High Rate Data Synchronization in GALS SoCs. IEEE Trans. VLSI Syst. 14(10): 1063-1074 (2006)

Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny: Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC 2006: 117-127

Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Efficient link capacity and QoS design for network-on-chip. DATE 2006: 9-14

Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar: Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Trans. VLSI Syst. 13(4): 427-438 (2005)

Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar: An Asynchronous Router for Multiple Service Levels Networks on Chip. ASYNC 2005: 44-53

Tsachy Kapschitz, Ran Ginosar: Formal Verification of Synchronizers. CHARME 2005: 359-362

Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Low-leakage repeaters for NoC interconnects. ISCAS (1) 2005: 600-603

Ilya Obridko, Ran Ginosar: Low energy asynchronous architectures. ISCAS (5) 2005: 5238-5241

Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Cost considerations in network on chip. Integration 38(1): 19-42 (2004)

Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture 50(2-3): 105-128 (2004)

Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar: Asynchronous gate-diffusion-input (GDI) circuits. IEEE Trans. VLSI Syst. 12(8): 847-856 (2004)

Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou: Data Synchronization Issues in GALS SoCs. ASYNC 2004: 170-180

Alex Branover, Rakefet Kol, Ran Ginosar: Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. DATE 2004: 870-877

Uri Frank, Ran Ginosar: A Predictive Synchronizer for Periodic Clock Domains. PATMOS 2004: 402-412

Ken S. Stevens, Ran Ginosar, Shai Rotem: Relative timing [asynchronous design]. IEEE Trans. VLSI Syst. 11(1): 129-140 (2003)

Y. Elboim, Avinoam Kolodny, Ran Ginosar: A clock-tuning circuit for system-on-chip. IEEE Trans. VLSI Syst. 11(4): 616-626 (2003)

Yaron Semiat, Ran Ginosar: Timing Measurements of Synchronization Circuits. ASYNC 2003: 68-77

Ran Ginosar: Fourteen Ways to Fool Your Synchronizer. ASYNC 2003: 89-97

Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun: RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70

Ken S. Stevens, Shai Rotem, Ran Ginosar: Relative Timing. ASYNC 1999: 208-218

Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken: CAD Directions for High Performance Asynchronous Circuits. DAC 1999: 116-121

Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun: Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80-

Ran Ginosar, Rakefet Kol: Adaptive synchronization. ICCD 1998: 188-189

Rakefet Kol, Ran Ginosar: Kin: A High Performance Asynchronous Processor Architecture. International Conference on Supercomputing 1998: 433-440

Uzi Zangi, Ran Ginosar: A low power video processor. ISLPED 1998: 136-138

Rakefet Kol, Ran Ginosar: A Double-Latched Asynchronous Pipeline. ICCD 1997: 706-712

Ilana David, Ran Ginosar, Michael Yoeli: Self-timed is self-checking. J. Electronic Testing 6(2): 219-228 (1995)

Alan Rotman, Ran Ginosar: Control unit synthesis from a high-level language. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 162-167 (1993)

Ilana David, Ran Ginosar, Michael Yoeli: Self-Timed Architecture of a Reduced Instruction Set Computer. Asynchronous Design Methodologies 1993: 29-43

Ilana David, Ran Ginosar, Michael Yoeli: An Efficient Implementation of Boolean Functions as Self-Timed Circuits. IEEE Trans. Computers 41(1): 2-11 (1992)

Ilana David, Ran Ginosar, Michael Yoeli: Implementing Sequential Machines as Self-Timed Circuits. IEEE Trans. Computers 41(1): 12-17 (1992)

Arie Harsat, Ran Ginosar: CARMEL-4: The Unify-Spawn Machine for FCP. ICLP 1991: 840-854

Arie Harsat, Ran Ginosar: CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog. New Generation Comput. 7(2-3): 197-218 (1990)

Arie Harsat, Ran Ginosar: An Extended RISC Methodology and its Application to FCP. ICLP 1990: 67-82

Ran Ginosar, David Egozi: Topological comparison of perfect shuffle and hypercube. International Journal of Parallel Programming 18(1): 37-68 (1989)

Arie Harsat, Ran Ginosar: CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog. FGCS 1988: 962-969

Ran Ginosar, Dwight D. Hill: Design and Implementation of Switching Systems for Parallel Processors. ICPP 1985: 674-680

Bruce W. Arden, Ran Ginosar: Performance evaluation of the MP/C. AFIPS National Computer Conference 1983: 539-555

Bruce W. Arden, Ran Ginosar: MP/C: A Multiprocessor/Computer Architecture. IEEE Trans. Computers 31(5): 455-473 (1982)

Bruce W. Arden, Ran Ginosar: MP/C: A Multiprocessor/Computer Architecture. ISCA 1981: 3-20

Bruce W. Arden, Ran Ginosar: A Single-Relation Module for a Data Base Machine. ISCA 1981: 227-238