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 | 2013 | |
|---|---|---|
| j41 |      | Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel: A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. VLSI Syst. 21(2): 306-319 (2013) |
| j40 | | Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel: Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. VLSI Syst. 21(5): 958-970 (2013) |
| c139 | | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine: Test solution for data retention faults in low-power SRAMs. DATE 2013: 442-447 |
| 2012 | ||
| j39 | | Junxia Ma, Mohammad Tehranipoor, Patrick Girard: A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk. J. Electronic Testing 28(2): 201-214 (2012) |
| j38 | | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez: Analysis and Fault Modeling of Actual Resistive Defects in ATMEL [InlineMediaObject not available: see fulltext.] eFlash Memories. J. Electronic Testing 28(2): 215-228 (2012) |
| j37 | | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electronic Testing 28(3): 317-329 (2012) |
| j36 | | Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen: Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns. J. Low Power Electronics 8(2): 248-258 (2012) |
| c138 | | Patrick Girard, Jeremy Seligman, Fenrong Liu: General Dynamic Dynamic Logic. Advances in Modal Logic 2012: 239-260 |
| c137 | | J. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay: Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. ATS 2012: 125-130 |
| c136 | | Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot: Power Supply Noise Sensor Based on Timing Uncertainty Measurements. ATS 2012: 161-166 |
| c135 | | Paolo Bernardi, M. De Carvalho, E. Sanchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka: Peak Power Estimation: A Case Study on CPU Cores. ATS 2012: 167-172 |
| c134 | | Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel: Why and How Controlling Power Consumption during Test: A Survey. ATS 2012: 221-226 |
| c133 | | J. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay: Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE 2012: 532-537 |
| c132 | | J. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay: Coupling-based resistive-open defects in TAS-MRAM architectures. European Test Symposium 2012: 1 |
| c131 | | C. Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel: Through-Silicon-Via resistive-open defect analysis. European Test Symposium 2012: 1 |
| c130 | | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine: Defect analysis in power mode control logic of low-power SRAMs. European Test Symposium 2012: 1 |
| c129 | | Thomas Lachaume, Patrick Girard, Laurent Guittet, Allan Fousse: ProtoTask, New Task Model Simulator. HCSE 2012: 323-330 |
| c128 | | Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné: Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS 2012: 121-122 |
| c127 | | Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang: On pinpoint capture power management in at-speed scan test generation. ITC 2012: 1-10 |
| c126 | | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine: Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC 2012: 1-10 |
| c125 | | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich: A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS 2012: 50-55 |
| c124 | | Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: Advanced test methods for SRAMs. VTS 2012: 300-301 |
| 2011 | ||
| j35 | | Sybille Caffiau, Patrick Girard, Laurent Guittet, Xavier Blanc: Vérification de cohérence entre modèles de tâches et de dialogue en conception centrée-utilisateur. Ingénierie des Systèmes d'Information 16(5): 9-41 (2011) |
| c123 | | Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel: Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95 |
| c122 | | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich: A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141 |
| c121 | | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine: Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium 2011: 459-460 |
| c120 | | Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, X. Wen: Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium 2011: 506-510 |
| c119 | | Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS 2011: 189-194 |
| c118 | | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS 2011: 353-358 |
| c117 | | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez: On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS 2011: 359-364 |
| c116 | | Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch: On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT 2011: 226-232 |
| c115 | | Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT 2011: 294-301 |
| c114 | | Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda: A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. European Test Symposium 2011: 153-158 |
| c113 | | |
| c112 | | Thomas Lachaume, Patrick Girard, Laurent Guittet, Allan Fousse: Prototypage basé sur les modèles de tâches: une étude pilote. IHM 2011: 23 |
| c111 | | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: On using address scrambling to implement defect tolerance in SRAMs. ITC 2011: 1-8 |
| c110 | | Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor: Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS 2011: 166-171 |
| 2010 | ||
| j34 | | Adrien Marion, Patrick Girard, Didier Vray: Quaternionic Spatiotemporal Filtering for Dense Motion Field Estimation in Ultrasound Imaging. EURASIP J. Adv. Sig. Proc. 2010 (2010) |
| j33 | | Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor: High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Transactions 93-D(1): 2-9 (2010) |
| j32 | | Sybille Caffiau, Dominique L. Scapin, Patrick Girard, Mickaël Baron, Francis Jambon: Increasing the expressive power of task analysis: Systematic comparison and empirical assessment of tool-supported task models. Interacting with Computers 22(6): 569-593 (2010) |
| j31 | | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed: A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electronics 6(2): 359-374 (2010) |
| j30 | | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers 59(3): 289-300 (2010) |
| c109 | | Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo: A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium 2010: 100-105 |
| c108 | | Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer: A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium 2010: 237-242 |
| c107 | | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: A statistical simulation method for reliability analysis of SRAM core-cells. DAC 2010: 853-856 |
| c106 | | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen: Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS 2010: 376-381 |
| c105 | | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda: An Exact and Efficient Critical Path Tracing Algorithm. DELTA 2010: 164-169 |
| c104 | | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA 2010: 265-269 |
| c103 | | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez: A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. European Test Symposium 2010: 81-86 |
| c102 | | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. European Test Symposium 2010: 132-137 |
| c101 | | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Setting test conditions for improving SRAM reliability. European Test Symposium 2010: 257 |
| c100 | | Junxia Ma, Jeremy Lee, Mohammad Tehranipoor, Nisar Ahmed, Patrick Girard: Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric. ACM Great Lakes Symposium on VLSI 2010: 127-130 |
| c99 | | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed: Is test power reduction through X-filling good enough? ITC 2010: 805 |
| c98 | | Jean Marc Gallière, Paolo Rech, Patrick Girard, Luigi Dilillo: A roaming memory test bench for detecting particle induced SEUs. ITC 2010: 810 |
| c97 | | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich: Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820 |
| c96 | | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine: Detecting NBTI induced failures in SRAM core-cells. VTS 2010: 75-80 |
| 2009 | ||
| j29 | | Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electronic Testing 25(2-3): 127-144 (2009) |
| j28 | | Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Is triple modular redundancy suitable for yield improvement? IET Computers & Digital Techniques 3(6): 581-592 (2009) |
| j27 | | Johan van Benthem, Patrick Girard, Olivier Roy: Everything Else Being Equal: A Modal Logic for Ceteris Paribus Preferences. J. Philosophical Logic 38(1): 83-125 (2009) |
| j26 | | Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Trans. VLSI Syst. 17(10): 1556-1559 (2009) |
| c95 | | Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer: Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium 2009: 355-360 |
| c94 | | Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin: A new design-for-test technique for SRAM core-cell stability faults. DATE 2009: 1344-1348 |
| c93 | | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda: An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS 2009: 50-55 |
| c92 | | Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute: Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS 2009: 264-269 |
| c91 | | Christophe Kolski, Peter Forbrig, Bertrand David, Patrick Girard, Chi Dung Tran, Houcine Ezzedine: Agent-Based Architecture for Interactive System Design: Current Approaches, Perspectives and Evaluation. HCI (1) 2009: 624-633 |
| c90 | | Sybille Caffiau, Patrick Girard, Laurent Guittet, Dominique L. Scapin: Hierarchical Structure: A Step for Jointly Designing Interactive Software Dialog and Task Model. HCI (2) 2009: 664-673 |
| c89 | | |
| c88 | | Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute: A case study on logic diagnosis for System-on-Chip. ISQED 2009: 253-259 |
| c87 | | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard: NAND flash testing: A preliminary study on actual defects. ITC 2009: 1 |
| c86 | | Sybille Caffiau, Patrick Girard, Dominique L. Scapin, Laurent Guittet, Loé Sanou: Formally Expressing the Users' Objects World in Task Models. TAMODIA 2009: 117-130 |
| 2008 | ||
| j25 | | |
| j24 | | Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault: A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electronic Testing 24(4): 353-364 (2008) |
| c85 | | Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen: Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008 |
| c84 | | Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin: A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE 2008: 1480-1485 |
| c83 | | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi: SoC Symbolic Simulation: a case study on delay fault testing. DDECS 2008: 320-325 |
| c82 | | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215 |
| c81 | | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Using TMR Architectures for Yield Improvement. DFT 2008: 7-15 |
| c80 |  | Patrick Girard, Vincent Thomson: Energy Model based Control for Forming Processes. ICINCO-ICSO 2008: 51-59 |
| c79 | | Loé Sanou, Patrick Girard, Laurent Guittet, Sybille Caffiau: Tester la conformité d'une IHM à son modèle de tâches. IHM 2008: 159-162 |
| c78 | | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS 2008: 165-166 |
| c77 | | Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC 2008: 1-10 |
| c76 | | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: SoC Yield Improvement: Redundant Architectures to the Rescue? ITC 2008: 1 |
| c75 | | Sybille Caffiau, Patrick Girard, Dominique L. Scapin, Laurent Guittet, Loé Sanou: Assessment of Object Use for Task Modeling. TAMODIA/HCSE 2008: 14-28 |
| c74 | | Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin: An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS 2008: 89-94 |
| 2007 | ||
| j23 | | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electronic Testing 23(5): 435-444 (2007) |
| c73 | | Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE 2007: 528-533 |
| c72 | | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242 |
| c71 | | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: DERRIC: A Tool for Unified Logic Diagnosis. European Test Symposium 2007: 13-20 |
| c70 | | Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. European Test Symposium 2007: 77-84 |
| c69 | | Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. European Test Symposium 2007: 97-104 |
| c68 | | Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga: A concurrent approach for testing address decoder faults in eFlash memories. ITC 2007: 1-10 |
| c67 | | Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang: A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC 2007: 1-10 |
| c66 | | Sybille Caffiau, Patrick Girard, Dominique L. Scapin, Laurent Guittet: Generating Interactive Applications from Task Models: A Hard Challenge. TAMODIA 2007: 267-272 |
| c65 | | Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS 2007: 47-52 |
| c64 | | Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS 2007: 361-368 |
| e2 | | Patrick Girard, Andrzej Krasniewski, Elena Gramatová, Adam Pawlak, Tomasz Garbolino (Eds.): Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), Kraków, Poland, April 11-13, 2007. IEEE Computer Society 2007, isbn 1-4244-1161-0 |
| 2006 | ||
| j22 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electronic Testing 22(1): 89-99 (2006) |
| j21 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing 22(2): 161-172 (2006) |
| j20 | | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan: ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electronic Testing 22(3): 287-296 (2006) |
| j19 | | Zahir Albadawi, Benoit Boulet, Robert DiRaddo, Patrick Girard, Alexandre Rail, Vincent Thomson: Agent-based control of manufacturing processes. IJMR 1(4): 466-481 (2006) |
| j18 | | Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard: Reducing Power Dissipation in SRAM during Test. J. Low Power Electronics 2(2): 271-280 (2006) |
| c63 | | Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard: Minimizing test power in SRAM through reduction of pre-charge activity. DATE 2006: 1159-1164 |
| c62 | | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS 2006: 256-261 |
| c61 | | Loé Sanou, Patrick Girard, Laurent Guittet: Comparaison de deux méthodes pour implémenter la programmation sur exemple. IHM 2006: 265-268 |
| c60 | | Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich: Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408 |
| c59 | | Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: An Overview of Failure Mechanisms in Embedded Flash Memories. VTS 2006: 108-113 |
| 2005 | ||
| j17 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electronic Testing 21(1): 43-55 (2005) |
| j16 | | Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electronic Testing 21(2): 169-179 (2005) |
| j15 | | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan: Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electronic Testing 21(5): 551-561 (2005) |
| j14 | | Patrick Girard: Welcome to the Journal of Low Power Electronics. J. Low Power Electronics 1(1): 1-2 (2005) |
| j13 | | Patrick Girard, Yannick Bonhomme: Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. J. Low Power Electronics 1(1): 85-95 (2005) |
| c58 | | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC 2005: 857-862 |
| c57 | | Nicolas Guibert, Laurent Guittet, Patrick Girard: Validation d'une approche " basée sur exemples " pour l'apprentissage de la programmation. IHM 2005: 147-154 |
| c56 | | Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault: Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS 2005: 540-549 |
| c55 | | Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault: Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC 2005: 267-281 |
| c54 | | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan: Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS 2005: 183-188 |
| 2004 | ||
| j12 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Power-Driven Routing-Constrained Scan Chain Design. J. Electronic Testing 20(6): 647-660 (2004) |
| c53 | | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan: Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium 2004: 266-271 |
| c52 | | Nicolas Guibert, Patrick Girard, Laurent Guittet: Example-based programming: a pertinent visual approach for learning to program. AVI 2004: 358-361 |
| c51 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67 |
| c50 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA 2004: 83-88 |
| c49 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294 |
| c48 | | Yamine Aït Ameur, Benoit Breholée, Patrick Girard, Laurent Guittet, Francis Jambon: Formal Verification and Validation of Interactive Systems Specifications. Human Error, Safety and Systems Development 2004: 61-76 |
| c47 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS 2004: 187-192 |
| c46 | | |
| c45 | | Benoit Boulet, Robert DiRaddo, Patrick Girard, Vincent Thomson: An agent based architecture for model based control. SMC (2) 2004: 2002-2007 |
| c44 | | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri: March iC-: An Improved Version of March C- for ADOFs Detection. VTS 2004: 129-138 |
| 2003 | ||
| j11 | | Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault: A Ring Architecture Strategy for BIST Test Pattern Generation. J. Electronic Testing 19(3): 223-231 (2003) |
| c43 | | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri: Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium 2003: 250-255 |
| c42 | | Mickaël Baron, Patrick Girard: SUIDT: a user interface builder for secure user interfaces. IHM 2003: 198-201 |
| c41 | | Nicolas Guibert, Patrick Girard: Programming by example and computer-aided teaching of algorithmics: the MELBA project. IHM 2003: 248-251 |
| c40 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS 2003: 124-128 |
| c39 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC 2003: 488-493 |
| c38 | | Yamine Aït Ameur, Mickaël Baron, Patrick Girard: Formal Validation of HCI User Tasks. Software Engineering Research and Practice 2003: 732-738 |
| 2002 | ||
| j10 | | Patrick Girard: Survey of Low-Power Testing of VLSI Circuits. IEEE Design & Test of Computers 19(3): 82-92 (2002) |
| j9 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich: High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Design & Test of Computers 19(5): 44-52 (2002) |
| j8 | | René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Hardware Generation of Random Single Input Change Test Sequences. J. Electronic Testing 18(2): 145-157 (2002) |
| c37 | | Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Test Power: a Big Issue in Large SOC Designs. DELTA 2002: 447-449 |
| c36 | | Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Power Driven Chaining of Flip-Flops in Scan Architectures. ITC 2002: 796-803 |
| c35 | | |
| c34 | | René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: On Using Efficient Test Sequences for BIST. VTS 2002: 145-152 |
| e1 | | Patrick Girard, Thomas Baudel, Michel Beaudouin-Lafon, Eric Lecolinet, Dominique L. Scapin (Eds.): Proceedings of the 14th French-speaking conference on Human-computer interactio n, Conference Francophone sur l'Interaction Homme-Machine, IHM 2002, Poitiers, France, November 26-29, 2002. ACM International Conference Proceeding Series 32, ACM 2002, isbn 1-58113-615-3 |
| 2001 | ||
| j7 | | Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electronic Testing 17(3-4): 233-241 (2001) |
| c33 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258 |
| c32 | | Francis Jambon, Patrick Girard, Yamine Aït Ameur: Interactive System Safety and Usability Enforced with the Development Process. EHCI 2001: 39-56 |
| c31 | | Guillaume Texier, Laurent Guittet, Patrick Girard: The dialog tool set: a new way to create the dialog component. HCI 2001: 200-204 |
| c30 | | René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC 2001: 413-424 |
| c29 | | Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW 2001: 87-89 |
| c28 | | |
| c27 | | Guillaume Patry, Patrick Girard: End-User Programming in a Structured Dialogue Environment: the GIPSE Project. HCC 2001: 212- |
| c26 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich: A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS 2001: 306-311 |
| 2000 | ||
| j6 | | Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Paulo J. Teixeira, Marcelino B. Santos: Low Power BIST by Filtering Non-Detecting Vectors. J. Electronic Testing 16(3): 193-202 (2000) |
| c25 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium 2000: 459-464 |
| c24 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW 2000: 121-126 |
| c23 | | |
| c22 | | Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch: Low power BIST design by hypergraph partitioning: methodology and architectures. ITC 2000: 652-661 |
| c21 | | Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault: Hidden Markov and Independence Models with Patterns for Sequential BIST. VTS 2000: 359-368 |
| 1999 | ||
| j5 | | Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel: A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electronic Testing 14(1-2): 95-102 (1999) |
| c20 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium 1999: 89-94 |
| c19 | | |
| c18 | | Francis Jambon, Patrick Girard, Yohann Boisdron: Dialogue Validation from Task Analysis. DSV-IS 1999: 205-224 |
| c17 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI 1999: 24- |
| c16 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Paulo J. Teixeira, Marcelino B. Santos: Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113 |
| c15 | | Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS 1999: 407-412 |
| 1998 | ||
| c14 | | Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault: A Ring Architecture Strategy for BIST Test Pattern Generation. Asian Test Symposium 1998: 418-423 |
| c13 | | Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel: A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium 1998: 435-439 |
| c12 | | Yamine Aït Ameur, Patrick Girard, Francis Jambon: A Uniform Approach for Specification and Design of Interactive Systems: the B Method. DSV-IS (2) 1998: 51-67 |
| c11 | | Yamine Aït Ameur, Patrick Girard, Francis Jambon: Using the B Formal Approach for Incremental Specification Design of Interactiv Systems. EHCI 1998: 91-109 |
| 1997 | ||
| j4 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac: A non-iterative gate resizing algorithm for high reduction in power consumption. Integration 24(1): 37-52 (1997) |
| c10 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac: A gate resizing technique for high reduction in power consumption. ISLPED 1997: 281-286 |
| c9 | | Christophe Fagot, Patrick Girard, Christian Landrault: On Using Machine Learning for Logic BIST. ITC 1997: 338-346 |
| c8 | | Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch: An optimized BIST test pattern generator for delay testing. VTS 1997: 94-100 |
| 1996 | ||
| c7 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC 1996: 286-293 |
| c6 | | S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: A new test pattern generation method for delay fault testing. VTS 1996: 296-301 |
| 1995 | ||
| j3 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch: An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electronic Testing 6(3): 277-294 (1995) |
| j2 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: Delay fault diagnosis in sequential circuits based on path tracing. Integration 19(3): 199-218 (1995) |
| c5 | | Yamine Aït Ameur, Frederic Besnard, Patrick Girard, Guy Pierra, Jean-Claude Potier: Formal Specification and Metaprogramming in the EXPRESS Language. SEKE 1995: 181-188 |
| c4 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS 1995: 380-386 |
| 1994 | ||
| c3 | | D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC 1994: 518-523 |
| 1993 | ||
| c2 | | D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC 1993: 705-713 |
| 1992 | ||
| j1 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Design & Test of Computers 9(4): 27-32 (1992) |
| c1 | | Patrick Girard, Christian Landrault, Serge Pravossoudovitch: A Novel Approach to Delay-Fault Diagnosis. DAC 1992: 357-360 |
Colors in the list of coauthors
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