| 2013 | ||
|---|---|---|
| c6 | Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier: FPGA latency optimization using system-level transformations and DFG restructuring. DATE 2013: 1553-1558 | |
| 2010 | ||
| c5 | Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon: Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. HLDVT 2010: 33-39 | |
| 2009 | ||
| j2 | Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon: High-Level Dataflow Transformations Using Taylor Expansion Diagrams. IEEE Design & Test of Computers 26(4): 46-57 (2009) | |
| j1 | Maciej J. Ciesielski, Daniel Gomez-Prado, Qian Ren, Jérémie Guillot, Emmanuel Boutillon: Optimization of Data-Flow Computations Using Canonical TED Representation. IEEE Trans. on CAD of Integrated Circuits and Systems 28(9): 1321-1333 (2009) | |
| c4 | Daniel Gomez-Prado, Qian Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon: Optimizing data flow graphs to minimize hardware implementation. DATE 2009: 117-122 | |
| 2007 | ||
| c3 | Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon: Data-flow transformations using Taylor expansion diagrams. DATE 2007: 455-460 | |
| 2006 | ||
| c2 | Jérémie Guillot, Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, Daniel Gomez-Prado, Serkan Askar: Efficient factorization of DSP transforms using taylor expansion diagrams. DATE 2006: 754-755 | |
| 2004 | ||
| c1 | Daniel Gomez-Prado, Qian Ren, Serkan Askar, Maciej J. Ciesielski, Emmanuel Boutillon: Variable ordering for taylor expansion diagrams. HLDVT 2004: 55-59 | |
| 1 | Serkan Askar | |
| 2 | Emmanuel Boutillon | |
| 3 | Maciej J. Ciesielski | |
| 4 | Jérémie Guillot | |
| 5 | Dusung Kim | |
| 6 | Qian Ren | |
| 7 | Russell Tessier |
Data released under the ODC-BY 1.0 license — See also our legal information page