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 | 2013 | |
|---|---|---|
| j13 |      | Wei Zang, Ann Gordon-Ross: T-SPaCS - A Two-Level Single-Pass Cache Simulation Methodology. IEEE Trans. Computers 62(2): 390-403 (2013) |
| c44 | | Aurelio Morales-Villanueva, Ann Gordon-Ross: HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs. ARC 2013: 185-196 |
| 2012 | ||
| j12 | | Weixun Wang, Prabhat Mishra, Ann Gordon-Ross: Dynamic Cache Reconfiguration for Soft Real-Time Systems. ACM Trans. Embedded Comput. Syst. 11(2): 28 (2012) |
| j11 | | Ann Gordon-Ross, Frank Vahid, Nikil Dutt: Combining code reordering and cache configuration. ACM Trans. Embedded Comput. Syst. 11(4): 88 (2012) |
| j10 | | Arslan Munir, Ann Gordon-Ross: An MDP-Based Dynamic Optimization Methodology for Wireless Sensor Networks. IEEE Trans. Parallel Distrib. Syst. 23(4): 616-625 (2012) |
| j9 | | Arslan Munir, Sanjay Ranka, Ann Gordon-Ross: High-Performance Energy-Efficient Multicore Embedded Computing. IEEE Trans. Parallel Distrib. Syst. 23(4): 684-700 (2012) |
| j8 | | Adam Jacobs, Grzegorz Cieslewski, Alan D. George, Ann Gordon-Ross, Herman Lam: Reconfigurable Fault Tolerance: A Comprehensive Framework for Reliable and Adaptive FPGA-Based Space Computing. TRETS 5(4): 21 (2012) |
| c43 | | Marisha Rawlins, Ann Gordon-Ross: An application classification guided cache tuning heuristic for multi-core architectures. ASP-DAC 2012: 23-28 |
| c42 | | Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky: Online algorithms for wireless sensor networks dynamic optimization. CCNC 2012: 180-187 |
| c41 | | Tosiron Adegbija, Ann Gordon-Ross, Arslan Munir: Dynamic phase-based tuning for embedded systems using phase distance mapping. ICCD 2012: 284-290 |
| c40 | | Arslan Munir, Ann Gordon-Ross, Sanjay Ranka: Parallelized benchmark-driven performance evaluation of SMPs and tiled multi-core architectures for embedded systems. IPCCC 2012: 416-423 |
| c39 | | Wei Zang, Ann Gordon-Ross: A single-pass cache simulation methodology for two-level unified caches. ISPASS 2012: 168-177 |
| 2011 | ||
| j7 | | Saleh Abdel-Hafeez, Ann Gordon-Ross: A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic. IEEE Trans. VLSI Syst. 19(6): 1023-1033 (2011) |
| c38 | | Abelardo Jara-Berrocal, Ann Gordon-Ross: An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips. ASAP 2011: 219-222 |
| c37 | | Marisha Rawlins, Ann Gordon-Ross: On the interplay of loop caching, code compression, and cache configuration. ASP-DAC 2011: 243-248 |
| c36 | | Wei Zang, Ann Gordon-Ross: T-SPaCS - A two-level single-pass cache simulation methodology. ASP-DAC 2011: 419-424 |
| c35 | | Abelardo Jara-Berrocal, Ann Gordon-Ross: Hardware module reuse and runtime assembly for dynamic management of reconfigurable resources. FPT 2011: 1-6 |
| c34 | | Rohit Kumar, Ann Gordon-Ross: Formulation-level design space exploration for partially reconfigurable FPGAs. FPT 2011: 1-6 |
| c33 | | Shaon Yousuf, Adam Jacobs, Ann Gordon-Ross: Partially reconfigurable system-on-chips for adaptive fault tolerance. FPT 2011: 1-8 |
| c32 | | Arslan Munir, Ann Gordon-Ross: Markov Modeling of Fault-Tolerant Wireless Sensor Networks. ICCCN 2011: 1-6 |
| c31 | | Arslan Munir, Ann Gordon-Ross, Sanjay Ranka: A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems. ICCD 2011: 198-205 |
| c30 | | Marisha Rawlins, Ann Gordon-Ross: CPACT - The conditional parameter adjustment cache tuner for dual-core architectures. ICCD 2011: 396-403 |
| 2010 | ||
| j6 | | Ashish Shenoy, Jeff Hiner, Susan Lysecky, Roman L. Lysecky, Ann Gordon-Ross: Evaluation of Dynamic Profiling Methodologies for Optimization of Sensor Networks. Embedded Systems Letters 2(1): 10-13 (2010) |
| j5 | | Arslan Munir, Ann Gordon-Ross: SIP-Based IMS Signaling Analysis for WiMax-3G Interworking Architectures. IEEE Trans. Mob. Comput. 9(5): 733-750 (2010) |
| c29 | | Abelardo Jara-Berrocal, Ann Gordon-Ross: VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems. DATE 2010: 837-842 |
| c28 |  | Ann Gordon-Ross, Abelardo Jara-Berrocal: VAPRES: A Customizable and Flexible Base Architecture for Partially Reconfigurable Systems. ERSA 2010: 67-76 |
| c27 | | Shaon Yousuf, Ann Gordon-Ross: DAPR: Design Automation for Partially Reconfigurable FPGAs. ERSA 2010: 97-103 |
| c26 | | Marisha Rawlins, Ann Gordon-Ross: Lightweight runtime control flow analysis for adaptive loop caching. ACM Great Lakes Symposium on VLSI 2010: 239-244 |
| c25 | | Jeff Hiner, Ashish Shenoy, Roman L. Lysecky, Susan Lysecky, Ann Gordon-Ross: Transaction-Level Modeling for Sensor Networks Using SystemC. SUTC/UMC 2010: 197-204 |
| c24 | | Arslan Munir, Ann Gordon-Ross, Susan Lysecky, Roman L. Lysecky: A lightweight dynamic optimization methodology for wireless sensor networks. WiMob 2010: 129-136 |
| 2009 | ||
| j4 | | Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt: Fast Configurable-Cache Tuning With a Unified Second-Level Cache. IEEE Trans. VLSI Syst. 17(1): 80-91 (2009) |
| c23 | | Arslan Munir, Ann Gordon-Ross: An MDP-based application oriented optimal policy for wireless sensor networks. CODES+ISSS 2009: 183-192 |
| c22 | | Abelardo Jara-Berrocal, Ann Gordon-Ross: SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems. DATE 2009: 268-273 |
| c21 | | Adam Flynn, Ann Gordon-Ross, Alan D. George: Bitstream relocation with local clock domains for partially reconfigurable FPGAs. DATE 2009: 300-303 |
| c20 | | Rafael Garcia, Ann Gordon-Ross, Alan D. George: Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks. FCCM 2009: 243-246 |
| c19 | | Rohit Kumar, Ann Gordon-Ross: Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs. FPL 2009: 525-529 |
| c18 | | Arslan Munir, Ann Gordon-Ross: SIP-Based IMS Registration Analysis for WiMax-3G Interworking Architectures. ICNS 2009: 432-437 |
| c17 | | Abelardo Jara-Berrocal, Ann Gordon-Ross: Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time. ReConFig 2009: 374-379 |
| c16 | | Weixun Wang, Prabhat Mishra, Ann Gordon-Ross: SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. VLSI Design 2009: 547-552 |
| 2008 | ||
| c15 | | Chris Conger, Ann Gordon-Ross, Alan D. George: Design Framework for Partial Run-Time FPGA Reconfiguration. ERSA 2008: 122-128 |
| c14 | | Pablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid: A table-based method for single-pass cache optimization. ACM Great Lakes Symposium on VLSI 2008: 71-76 |
| c13 | | Ann Gordon-Ross, Jeremy Lau, Brad Calder: Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy. ACM Great Lakes Symposium on VLSI 2008: 379-382 |
| c12 | | Karthik Sabhanatarajan, Ann Gordon-Ross: A resource efficient content inspection system for next generation Smart NICs. ICCD 2008: 156-163 |
| c11 | | Karthik Sabhanatarajan, Ann Gordon-Ross, Mark Oden, Mukund Navada, Alan D. George: Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices. ISVLSI 2008: 75-80 |
| c10 | | Baoke Zhang, Karthik Sabhanatarajan, Ann Gordon-Ross, Alan D. George: Real-time performance analysis of Adaptive Link Rate. LCN 2008: 282-288 |
| 2007 | ||
| c9 | | |
| c8 | | Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros: A one-shot configurable-cache tuner for improved energy and performance. DATE 2007: 755-760 |
| 2006 | ||
| c7 | | Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid: Configurable cache subsetting for fast cache tuning. DAC 2006: 695-700 |
| 2005 | ||
| j3 | | Ann Gordon-Ross, Frank Vahid: Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware. IEEE Trans. Computers 54(10): 1203-1215 (2005) |
| c6 | | Ann Gordon-Ross, Frank Vahid, Nikil Dutt: A first look at the interplay of code reordering and configurable caches. ACM Great Lakes Symposium on VLSI 2005: 416-421 |
| c5 | | Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt: Fast configurable-cache tuning with a unified second-level cache. ISLPED 2005: 323-326 |
| 2004 | ||
| c4 | | Ann Gordon-Ross, Frank Vahid, Nikil Dutt: Automatic Tuning of Two-Level Caches to Embedded Applications. DATE 2004: 208-213 |
| 2003 | ||
| j2 | | Ann Gordon-Ross, Susan Cotterell, Frank Vahid: Tiny instruction caches for low power embedded systems. ACM Trans. Embedded Comput. Syst. 2(4): 449-481 (2003) |
| c3 | | Ann Gordon-Ross, Frank Vahid: Frequent loop detection using efficient non-intrusive on-chip hardware. CASES 2003: 117-124 |
| 2002 | ||
| j1 | | Ann Gordon-Ross, Susan Cotterell, Frank Vahid: Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example. Computer Architecture Letters 1 (2002) |
| c2 | | Ann Gordon-Ross, Frank Vahid: Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach. ICCD 2002: 446-449 |
| 2001 | ||
| c1 | | Frank Vahid, Ann Gordon-Ross: A self-optimizing embedded microprocessor using a loop table for low power. ISLPED 2001: 219-224 |
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