Paul V. Gratz
List of publications from the DBLP Bibliography Server - FAQ| 2012 | ||
|---|---|---|
| j4 | Reena Panda, Paul V. Gratz, Daniel A. Jimenez: B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors. Computer Architecture Letters 11(2): 41-44 (2012) | |
| c11 | Cheng Li, Mark Browning, Paul V. Gratz, Samuel Palermo: LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures. PACT 2012: 421-422 | |
| c10 | Yoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul Gratz: WaveSync: A low-latency source synchronous bypass network-on-chip architecture. ICCD 2012: 241-248 | |
| c9 | Yoon Seok Yang, Hrishikesh Deshpande, Gwan S. Choi, Paul Gratz: Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router. ISCAS 2012: 2433-2436 | |
| 2011 | ||
| j3 | Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson, Gwan Choi: Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1663-1676 (2011) | |
| c8 | Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz, Daniel A. Jimenez: Reducing network-on-chip energy consumption through spatial locality speculation. NOCS 2011: 233-240 | |
| c7 | Swapnil Lotlikar, Vinayak Pai, Paul V. Gratz: AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation. VLSI Design 2011: 147-152 | |
| 2010 | ||
| j2 | Hyungjun Kim, Paul V. Gratz: Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect. Computer Architecture Letters 9(1): 33-36 (2010) | |
| c6 | Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi: Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs. NOCS 2010: 51-58 | |
| 2009 | ||
| c5 | Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeffrey R. Diamond, Paul Gratz, Mario Marino, Nitya Ranganathan, Behnam Robatmili, Aaron Smith, James H. Burrill, Stephen W. Keckler, Doug Burger, Kathryn S. McKinley: An evaluation of the TRIPS computer system. ASPLOS 2009: 1-12 | |
| 2008 | ||
| c4 | Paul Gratz, Boris Grot, Stephen W. Keckler: Regional congestion awareness for load balance in networks-on-chip. HPCA 2008: 203-214 | |
| 2007 | ||
| j1 | Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger: On-Chip Interconnection Networks of the TRIPS Chip. IEEE Micro 27(5): 41-50 (2007) | |
| c3 | Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger: Implementation and Evaluation of a Dynamically Routed Processor Operand Network. NOCS 2007: 7-17 | |
| 2006 | ||
| c2 | Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger: Implementation and Evaluation of On-Chip Network Architectures. ICCD 2006 | |
| c1 | Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger: Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. MICRO 2006: 480-491 | |
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