| 2001 | ||
|---|---|---|
| c4 | Matt Postiff, David A. Greene, Steven E. Raasch, Trevor N. Mudge: Integrating superscalar processor components to implement register caching. ICS 2001: 348-357 | |
| 2000 | ||
| c3 | Matt Postiff, David A. Greene, Trevor N. Mudge: The store-load address table and speculative register promotion. MICRO 2000: 235-244 | |
| 1999 | ||
| j1 | Matthew A. Postiff, David A. Greene, Gary S. Tyson, Trevor N. Mudge: The limits of instruction level parallelism in SPEC95 applications. SIGARCH Computer Architecture News 27(1): 31-34 (1999) | |
| 1994 | ||
| c2 | ||
| 1993 | ||
| c1 | ||
| 1 | Trevor N. Mudge | |
| 2 | Matt Postiff (Matthew A. Postiff) | |
| 3 | Steven E. Raasch | |
| 4 | Gary S. Tyson |
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