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 | 2013 | |
|---|---|---|
| c58 |      | Hoang M. Le, Daniel Große, Rolf Drechsler: Scalable fault localization for SystemC TLM designs. DATE 2013: 35-38 |
| 2012 | ||
| j9 | | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. Multiple-Valued Logic and Soft Computing 19(4): 361-378 (2012) |
| j8 | | Hoang M. Le, Daniel Große, Rolf Drechsler: Automatic TLM Fault Localization for SystemC. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1249-1262 (2012) |
| c57 | | Marcio F. da S. Oliveira, Christoph Kuznik, Hoang M. Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen: The system verification methodology for advanced TLM verification. CODES+ISSS 2012: 313-322 |
| c56 | | Finn Haedicke, Daniel Große, Rolf Drechsler: A guiding coverage metric for formal verification. DATE 2012: 617-622 |
| c55 | | Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler: Coverage-Driven Stimuli Generation. DSD 2012: 525-528 |
| c54 | | Marc Michael, Daniel Große, Rolf Drechsler: Localizing features of ESL models for design understanding. FDL 2012: 120-125 |
| c53 | | Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille: Completeness-Driven Development. ICGT 2012: 38-50 |
| c52 |  | Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler: CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC. MBMV 2012: 37-48 |
| 2011 | ||
| j7 | | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging reversible circuits. Integration 44(1): 51-61 (2011) |
| c51 | | Mohamed Bawadekji, Daniel Große, Rolf Drechsler: TLM protocol compliance checking at the Electronic System Level. DDECS 2011: 435-440 |
| c50 | | Marc Michael, Daniel Große, Rolf Drechsler: Analyzing dependability measures at the Electronic System Level. FDL 2011: 1-8 |
| c49 | | Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler: Simulation-based equivalence checking between SystemC models at different levels of abstraction. ACM Great Lakes Symposium on VLSI 2011: 223-228 |
| c48 | | Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler: Designing a RISC CPU in Reversible Logic. ISMVL 2011: 170-175 |
| c47 | | Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler: Designing a RISC CPU in Reversible Logic. MBMV 2011: 249-258 |
| c46 | | Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler: Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction. MBMV 2011: 269-278 |
| 2010 | ||
| b1 | | |
| j6 | | Ulrich Kühne, Daniel Große, Rolf Drechsler: Towards Fully Automatic Synthesis of Embedded Software. Embedded Systems Letters 2(3): 53-57 (2010) |
| c45 | | Hoang M. Le, Daniel Große, Rolf Drechsler: Towards analyzing functional coverage in SystemC TLM property checking. HLDVT 2010: 67-74 |
| c44 | | Daniel Große, Hoang M. Le, Rolf Drechsler: Proving transaction and system-level properties of untimed SystemC TLM designs. MEMOCODE 2010: 113-122 |
| c43 | | Hoang M. Le, Daniel Große, Rolf Drechsler: Automatic Fault Localization for SystemC TLM Designs. MTV 2010: 35-40 |
| 2009 | ||
| j5 | | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits. Multiple-Valued Logic and Soft Computing 15(4): 283-300 (2009) |
| j4 | | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 703-715 (2009) |
| c42 | | Ulrich Kühne, Daniel Große, Rolf Drechsler: Property analysis and design understanding. DATE 2009: 1246-1249 |
| c41 | | Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler: Debugging of Toffoli networks. DATE 2009: 1284-1289 |
| c40 | | Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler: SMT-based stimuli generation in the SystemC Verification library. FDL 2009: 1-6 |
| c39 | | Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler: Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI 2009: 173-176 |
| c38 | | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. ISMVL 2009: 324-330 |
| c37 | | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler: Equivalence Checking of Reversible Circuits. MBMV 2009: 67-76 |
| c36 | | Daniel Große, Hoang M. Le, Rolf Drechsler: Induction-Based Formal Verification of SystemC TLM Designs. MTV 2009: 101-106 |
| c35 | | André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler: WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17 |
| c34 | | Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler: Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194 |
| 2008 | ||
| j3 | | Daniel Große, Ulrich Kühne, Rolf Drechsler: Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1305-1314 (2008) |
| c33 | | Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große: Quantified Synthesis of Reversible Logic. DATE 2008: 1015-1020 |
| c32 | | Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler: Contradiction Analysis for Constraint-based Random Simulation. FDL 2008: 130-135 |
| c31 | | Daniel Große: Quality-Driven Design and Verification Flow for Digital Systems. Ausgezeichnete Informatikdissertationen 2008: 121-130 |
| c30 | | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler: Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219 |
| c29 | | Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler: RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225 |
| c28 | | Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler: Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI 2008: 411-416 |
| c27 | | Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler: Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. MBMV 2008: 169-178 |
| c26 | | Ulrich Kühne, Daniel Große, Rolf Drechsler: Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. MTV 2008: 88-93 |
| 2007 | ||
| c25 | | Daniel Große, Ulrich Kühne, Rolf Drechsler: Estimating functional coverage in bounded model checking. DATE 2007: 1176-1181 |
| c24 | | Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler: Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. FDL 2007: 146-151 |
| c23 | | Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler: Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101 |
| c22 | | Daniel Große, Rüdiger Ebendt, Rolf Drechsler: Improvements for constraint solving in the systemc verification library. ACM Great Lakes Symposium on VLSI 2007: 493-496 |
| c21 | | Robert Wille, Daniel Große: Fast exact Toffoli network synthesis of reversible logic. ICCAD 2007: 60-64 |
| c20 | | Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler: Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ISMVL 2007: 50 |
| c19 | | Ulrich Kühne, Daniel Große, Rolf Drechsler: Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI 2007: 165-170 |
| c18 | | Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler: Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV 2007: 81-90 |
| c17 | | Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler: SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93 |
| 2006 | ||
| c16 | | Görschwin Fey, Daniel Große, Rolf Drechsler: Avoiding false negatives in formal verification for protocol-driven blocks. DATE 2006: 1225-1226 |
| c15 | | Daniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI 2006: 43-48 |
| 2005 | ||
| c14 | | Daniel Große, Rolf Drechsler: Acceleration of SAT-Based Iterative Property Checking. CHARME 2005: 349-353 |
| c13 | | Daniel Große, Ulrich Kühne, Rolf Drechsler: Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) 2005: 308-312 |
| c12 | | Daniel Große, Rolf Drechsler: CheckSyC: an efficient property checker for RTL SystemC designs. ISCAS (4) 2005: 4167-4170 |
| c11 | | Daniel Große, Ulrich Kühne, Rolf Drechsler: HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV 2005: 133-137 |
| c10 | | Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große: SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping 2005: 258-260 |
| 2004 | ||
| c9 | | |
| 2003 | ||
| j2 | | Daniel Große, Rolf Drechsler: Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it - Information Technology 45(4): 219-226 (2003) |
| c8 | | Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst: Efficient Automatic Visualization of SystemC Designs. FDL 2003: 646-658 |
| c7 | | |
| c6 | | Daniel Große, Rolf Drechsler: Formal verification of LTL formulas for SystemC designs. ISCAS (5) 2003: 245-248 |
| c5 | | Daniel Große, Görschwin Fey, Rolf Drechsler: Modeling Multi-Valued Circuits in SystemC. ISMVL 2003: 281-286 |
| c4 | | Daniel Große, Rolf Drechsler: Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen. MBMV 2003: 229-238 |
| 2002 | ||
| j1 | | Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. Genetic Programming and Evolvable Machines 3(4): 363-388 (2002) |
| c3 | | Rolf Drechsler, Daniel Große: Reachability Analysis for Formal Verification of SystemC. DSD 2002: 337-340 |
| 2001 | ||
| c2 | | Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler: Heuristic Learning Based on Genetic Programming. EuroGP 2001: 1-10 |
| c1 | | Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker: Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. Fuzzy Days 2001: 479-491 |
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