| 2012 | ||
|---|---|---|
| c7 | Victor W. Lee, Ed Grochowski, Robert Geva: Performance Benefits of Heterogeneous Computing in HPC Workloads. IPDPS Workshops 2012: 16-26 | |
| 2009 | ||
| j3 | Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Pradeep Dubey, Stephen Junkins, Adam Lake, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Michael Abrash, Jeremy Sugerman, Pat Hanrahan: Larrabee: A Many-Core x86 Architecture for Visual Computing. IEEE Micro 29(1): 10-21 (2009) | |
| 2008 | ||
| j2 | Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan: Larrabee: a many-core x86 architecture for visual computing. ACM Trans. Graph. 27(3) (2008) | |
| c6 | Ed Grochowski, Murali Annavaram, Paul Reed: Implications of device timing variability on full chip timing. ISPD 2008: 68 | |
| 2007 | ||
| c5 | Murali Annavaram, Ed Grochowski, Paul Reed: Implications of Device Timing Variability on Full Chip Timing. HPCA 2007: 37-45 | |
| 2005 | ||
| c4 | Murali Annavaram, Ed Grochowski, John Paul Shen: Mitigating Amdahl's Law through EPI Throttling. ISCA 2005: 298-309 | |
| 2004 | ||
| c3 | Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang: Best of Both Latency and Throughput. ICCD 2004: 236-243 | |
| 2003 | ||
| j1 | Ed Grochowski, David Ayers, Vivek Tiwari: Microarchitectural dI/dt Control. IEEE Design & Test of Computers 20(3): 40-47 (2003) | |
| 2002 | ||
| c2 | Ed Grochowski, David Ayers, Vivek Tiwari: Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation. HPCA 2002: 7-16 | |
| c1 | Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen: Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. HPCA 2002: 187-196 | |
Colors in the list of coauthors
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