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 | 2012 | |
|---|---|---|
| j11 |      | Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography. Int. J. Reconfig. Comp. 2012 (2012) |
| j10 | | M. Abdelaziz Elaabid, Sylvain Guilley: Portability of templates. J. Cryptographic Engineering 2(1): 63-74 (2012) |
| c65 | | Houssem Maghrebi, Claude Carlet, Sylvain Guilley, Jean-Luc Danger: Optimal First-Order Masking with Linear and Non-linear Bijections. AFRICACRYPT 2012: 360-377 |
| c64 | | Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache: Low-Cost Countermeasure against RPA. CARDIS 2012: 106-122 |
| c63 | | Sébastien Briais, Stéphane Caron, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, Jacques-Henri Jourdan, Arthur Milchior, David Naccache, Thibault Porteboeuf: 3D Hardware Canaries. CHES 2012: 1-22 |
| c62 | | Cédric Murdica, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst, David Naccache: Same Values Power Analysis Using Special Points on Elliptic Curves. COSADE 2012: 183-198 |
| c61 | | Houssem Maghrebi, Emmanuel Prouff, Sylvain Guilley, Jean-Luc Danger: A First-Order Leak-Free Masking Countermeasure. CT-RSA 2012: 156-170 |
| c60 | | Youssef Souissi, Shivam Bhasin, Sylvain Guilley, Maxime Nassar, Jean-Luc Danger: Towards Different Flavors of Combined Side Channel Attacks. CT-RSA 2012: 245-259 |
| c59 | | Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger: RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs. DATE 2012: 1173-1178 |
| c58 | | Zouha Cherif, Jean-Luc Danger, Sylvain Guilley, Lilian Bossuet: An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF. DSD 2012: 156-162 |
| c57 | | Sébastien Briais, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, David Naccache, Thibault Porteboeuf: Random Active Shield. FDTC 2012: 103-113 |
| c56 | | Houssem Maghrebi, Sylvain Guilley, Emmanuel Prouff, Jean-Luc Danger: Register leakage masking using Gray code. HOST 2012: 37-42 |
| c55 | | Houssem Maghrebi, Olivier Rioul, Sylvain Guilley, Jean-Luc Danger: Comparison between Side-Channel Analysis Distinguishers. ICICS 2012: 331-340 |
| c54 | | Sylvain Guilley, Jean-Luc Danger, Robert Nguyen, Philippe Nguyen: System-Level Methods to Prevent Reverse-Engineering, Cloning, and Trojan Insertion. ICISTM 2012: 433-438 |
| c53 | | Claude Carlet, Jean-Luc Danger, Sylvain Guilley, Houssem Maghrebi: Leakage Squeezing of Order Two. INDOCRYPT 2012: 120-139 |
| c52 | | Youssef Souissi, Nicolas Debande, Sami Mekki, Sylvain Guilley, Ali Maalaoui, Jean-Luc Danger: On the Optimality of Correlation Power Attack on Embedded Cryptographic Systems. WISTP 2012: 169-178 |
| i12 | | Houssem Maghrebi, Emmanuel Prouff, Sylvain Guilley, Jean-Luc Danger: A First-Order Leak-Free Masking Countermeasure. IACR Cryptology ePrint Archive 2012: 28 (2012) |
| i11 | | Houssem Maghrebi, Claude Carlet, Sylvain Guilley, Jean-Luc Danger: Optimal First-Order Masking with Linear and Non-Linear Bijections. IACR Cryptology ePrint Archive 2012: 175 (2012) |
| i10 | | Sébastien Briais, Stéphane Caron, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, Jacques-Henri Jourdan, Arthur Milchior, David Naccache, Thibault Porteboeuf: 3D Hardware Canaries. IACR Cryptology ePrint Archive 2012: 324 (2012) |
| i9 | | Sébastien Briais, Sylvain Guilley, Jean-Luc Danger: A formal study of two physical countermeasures against side channel attacks. IACR Cryptology ePrint Archive 2012: 430 (2012) |
| i8 | | Claude Carlet, Jean-Luc Danger, Sylvain Guilley, Houssem Maghrebi: Leakage Squeezing of Order Two. IACR Cryptology ePrint Archive 2012: 567 (2012) |
| 2011 | ||
| j9 | | Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger: Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks. IET Information Security 5(4): 181-190 (2011) |
| c51 | | Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar: Embedded systems security: An evaluation methodology against Side Channel Attacks. DASIP 2011: 230-237 |
| c50 | | Olivier Meynard, Denis Réal, Florent Flament, Sylvain Guilley, Naofumi Homma, Jean-Luc Danger: Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques. DATE 2011: 1004-1009 |
| c49 | | Houssem Maghrebi, Sylvain Guilley, Jean-Luc Danger: Formal security evaluation of hardware Boolean masking against second-order attacks. HOST 2011: 40-46 |
| c48 | | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Denis Réal: Performance evaluation of protocols resilient to physical attacks. HOST 2011: 51-56 |
| c47 | | Maxime Nassar, Sylvain Guilley, Jean-Luc Danger: Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. INDOCRYPT 2011: 22-39 |
| c46 | | Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger: "Rank Correction": A New Side-Channel Approach for Secret Key Recovery. InfoSecHiComNet 2011: 128-143 |
| c45 | | Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger: Efficient Dual-Rail Implementations in FPGA Using Block RAMs. ReConFig 2011: 261-267 |
| c44 | | Nicolas Debande, Youssef Souissi, Maxime Nassar, Sylvain Guilley, Thanh-Ha Le, Jean-Luc Danger: "Re-synchronization by moments": An efficient solution to align Side-Channel traces. WIFS 2011: 1-6 |
| c43 | | Sylvain Guilley, Karim Khalfallah, Victor Lomné, Jean-Luc Danger: Formal Framework for the Evaluation of Waveform Resynchronization Algorithms. WISTP 2011: 100-115 |
| c42 | | Houssem Maghrebi, Sylvain Guilley, Jean-Luc Danger: Leakage Squeezing Countermeasure against High-Order Attacks. WISTP 2011: 208-223 |
| c41 | | Manuel San Pedro, Mate Soos, Sylvain Guilley: FIRE: Fault Injection for Reverse Engineering. WISTP 2011: 280-293 |
| e1 | | Luca Breveglieri, Sylvain Guilley, Israel Koren, David Naccache, Junko Takahashi (Eds.): 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2011, Tokyo, Japan, September 29, 2011. IEEE 2011, isbn 978-1-4577-1463-4 |
| i7 | | Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback. CoRR abs/1103.1360 (2011) |
| i6 | | |
| i5 | | Houssem Maghrebi, Sylvain Guilley, Claude Carlet, Jean-Luc Danger: Classification of High-Order Boolean Masking Schemes and Improvements of their Efficiency. IACR Cryptology ePrint Archive 2011: 520 (2011) |
| i4 | | Maxime Nassar, Sylvain Guilley, Jean-Luc Danger: Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks. IACR Cryptology ePrint Archive 2011: 534 (2011) |
| 2010 | ||
| j8 | | Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfig. Comp. 2010 (2010) |
| j7 | | Sylvain Guilley, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, Renaud Pacalet: Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics. IEEE Trans. Computers 59(9): 1250-1263 (2010) |
| c40 | | M. Abdelaziz Elaabid, Sylvain Guilley: Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator. AFRICACRYPT 2010: 243-260 |
| c39 | | Shivam Bhasin, Sylvain Guilley, Florent Flament, Nidhal Selmane, Jean-Luc Danger: Countering early evaluation: an approach towards robust dual-rail precharge logic. WESS 2010: 6 |
| c38 | | Olivier Meynard, Denis Réal, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Frédéric Valette: Characterization of the Electromagnetic Side Channel in Frequency Domain. Inscrypt 2010: 471-486 |
| c37 | | Shivam Bhasin, Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger: Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks. CT-RSA 2010: 195-207 |
| c36 | | Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley: BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. DATE 2010: 849-854 |
| c35 | | Olivier Meynard, Sylvain Guilley, Jean-Luc Danger, Laurent Sauvage: Far Correlation-based EMA with a precharacterized leakage model. DATE 2010: 977-980 |
| c34 | | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane: Fault Injection Resilience. FDTC 2010: 51-65 |
| c33 | | Houssem Maghrebi, Sylvain Guilley, Jean-Luc Danger, Florent Flament: Entropy-based Power Attack. HOST 2010: 1-6 |
| c32 | | Youssef Souissi, Sylvain Guilley, Jean-Luc Danger, Sami Mekki, Guillaume Duc: Improvement of power analysis attacks using Kalman filter. ICASSP 2010: 1778-1781 |
| c31 | | Youssef Souissi, Maxime Nassar, Sylvain Guilley, Jean-Luc Danger, Florent Flament: First Principal Components Analysis: A New Side Channel Distinguisher. ICISC 2010: 407-419 |
| c30 | | Sylvain Guilley, Laurent Sauvage, Julien Micolod, Denis Réal, Frédéric Valette: Defeating Any Secret Cryptography with SCARE Attacks. LATINCRYPT 2010: 273-293 |
| c29 | | Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: Cross-Correlation Cartography. ReConFig 2010: 268-273 |
| c28 | | Zouha Cherif, Florent Flament, Jean-Luc Danger, Shivam Bhasin, Sylvain Guilley, Hervé Chabanne: Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA. ReConFig 2010: 310-315 |
| c27 | | M. Abdelaziz Elaabid, Olivier Meynard, Sylvain Guilley, Jean-Luc Danger: Combined Side-Channel Attacks. WISA 2010: 175-190 |
| i3 | | M. Abdelaziz Elaabid, Sylvain Guilley: Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator. IACR Cryptology ePrint Archive 2010: 116 (2010) |
| 2009 | ||
| j6 | | Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst: High speed true random number generator based on open loop structures in FPGAs. Microelectronics Journal 40(11): 1650-1656 (2009) |
| j5 | | Laurent Sauvage, Sylvain Guilley, Yves Mathieu: Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. TRETS 2(1) (2009) |
| c26 | | Mohaned Kafi, Sylvain Guilley, Sandra Marcello, David Naccache: Deconvolving Protected Signals. ARES 2009: 687-694 |
| c25 | | Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar: Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE 2009: 640-645 |
| c24 | | Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger: WDDL is Protected against Setup Time Violation Attacks. FDTC 2009: 73-83 |
| c23 | | Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Nidhal Selmane: Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs. HOST 2009: 15-21 |
| c22 | | Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. ICECS 2009: 351-354 |
| c21 | | Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane: Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218 |
| c20 | | Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu: DPL on Stratix II FPGA: What to Expect?. ReConFig 2009: 243-248 |
| 2008 | ||
| j4 | | Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri: Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. IEEE Trans. Computers 57(11): 1482-1497 (2008) |
| c19 | | Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98 |
| c18 | | Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger: An 8x8 run-time reconfigurable FPGA embedded in a SoC. DAC 2008: 120-125 |
| c17 | | Nidhal Selmane, Sylvain Guilley, Jean-Luc Danger: Practical Setup Time Violation Attacks on AES. EDCC 2008: 91-96 |
| c16 | | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet: Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC 2008: 3-17 |
| c15 | | Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley: Efficient tiling patterns for reconfigurable gate arrays. FPGA 2008: 257 |
| c14 | | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst: Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. FPL 2008: 161-166 |
| c13 | | Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong: Place-and-Route Impact on the Security of DPL Designs in FPGAs. HOST 2008: 26-32 |
| c12 | | Farouk Khelil, Mohamed Hamdi, Sylvain Guilley, Jean-Luc Danger, Nidhal Selmane: Fault Analysis Attack on an FPGA AES Implementation. NTMS 2008: 1-5 |
| c11 | | Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger: Efficient tiling patterns for reconfigurable gate arrays. SLIP 2008: 11-18 |
| c10 | | Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu: Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI 2008: 16-23 |
| i2 | | Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks. CoRR abs/0809.3942 (2008) |
| 2007 | ||
| j3 | | Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu: Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. IEEE Design & Test of Computers 24(6): 546-555 (2007) |
| j2 | | Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet: A fast pipelined multi-mode DES architecture operating in IP representation. Integration 40(4): 479-489 (2007) |
| c9 | | Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley: Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. FPL 2007: 665-669 |
| c8 | | Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst: A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT 2007: 369-372 |
| c7 |  | Philippe Hoogvorst, Sylvain Guilley, Sumanta Chaudhuri, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet: A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. ReCoSoC 2007: 15-22 |
| c6 | | Qing Xu, M. B. C. Silva, Jean-Luc Danger, Sylvain Guilley, Patrick Bellot, Philippe Gallion, Francisco Mendieta: Towards Quantum Key Distribution System using Homodyne Detection with Differential Time-Multiplexed Reference. RIVF 2007: 158-165 |
| i1 | | M. Abdelaziz Elaabid, Sylvain Guilley, Philippe Hoogvorst: Template Attacks with a Power Model. IACR Cryptology ePrint Archive 2007: 443 (2007) |
| 2006 | ||
| c5 | | Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst: FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. ReConFig 2006: 47-55 |
| 2005 | ||
| c4 | | Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet: The "Backend Duplication" Method. CHES 2005: 383-397 |
| c3 | | Sylvain Guilley, Philippe Hoogvorst: The Proof by 2M-1: a Low-Cost Method to Check Arithmetic Computations. SEC 2005: 589-600 |
| 2004 | ||
| j1 | | Sylvain Guilley, Renaud Pacalet: SoCs security: a war against side-channels. Annales des Télécommunications 59(7-8): 998-1009 (2004) |
| c2 | | Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet: Differential Power Analysis Model and Some Results. CARDIS 2004: 127-142 |
| c1 | | Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost: CMOS Structures Suitable for Secured Hardware. DATE 2004: 1414-1415 |
Colors in the list of coauthors
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