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 | 2010 | |
|---|---|---|
| j6 |      | Kanupriya Gulati, Sunil P. Khatri: Fault Table Computation on GPUs. J. Electronic Testing 26(2): 195-209 (2010) |
| c22 | | Kanupriya Gulati, Sunil P. Khatri: Boolean satisfiability on a graphics processor. ACM Great Lakes Symposium on VLSI 2010: 123-126 |
| 2009 | ||
| j5 | | Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: Selective Forward Body Bias for High Speed and Low Power SRAMs. J. Low Power Electronics 5(2): 185-195 (2009) |
| j4 | | Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas: FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2) (2009) |
| c21 | | Kanupriya Gulati, Sunil P. Khatri: Accelerating statistical static timing analysis using graphics processing units. ASP-DAC 2009: 260-265 |
| c20 | | Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry: Fast circuit simulation on graphics processing units. ASP-DAC 2009: 403-408 |
| c19 | | Kanupriya Gulati, Sunil P. Khatri, Peng Li: Closed-loop modeling of power and temperature profiles of FPGAs. FPGA 2009: 287 |
| c18 | | Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri: Robust window-based multi-node technology-independent logic minimization. ACM Great Lakes Symposium on VLSI 2009: 357-362 |
| c17 | | Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: Low power and high performance sram design using bank-based selective forward body bias. ACM Great Lakes Symposium on VLSI 2009: 441-444 |
| c16 | | Kanupriya Gulati, Sunil P. Khatri: Fault table generation using Graphics Processing Units. HLDVT 2009: 60-67 |
| c15 | | Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri: On-chip bidirectional wiring for heavily pipelined systems using network coding. ICCD 2009: 131-136 |
| c14 | | Srikanth Alaparthi, Kanupriya Gulati, Sunil P. Khatri: Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation. ISCAS 2009: 2225-2228 |
| 2008 | ||
| j3 | | Kanupriya Gulati, Mandar Waghmode, Sunil P. Khatri, Weiping Shi: Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Computers & Digital Techniques 2(3): 214-229 (2008) |
| j2 | | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker: A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration 41(3): 399-412 (2008) |
| j1 | | Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri: SAT-based ATPG using multilevel compatible don't-cares. ACM Trans. Design Autom. Electr. Syst. 13(2) (2008) |
| c13 | | Kanupriya Gulati, Sunil P. Khatri: Towards acceleration of fault simulation using graphics processing units. DAC 2008: 822-827 |
| c12 | | Kanupriya Gulati, Sunil P. Khatri: Improving FPGA routability using network coding. ACM Great Lakes Symposium on VLSI 2008: 147-150 |
| 2007 | ||
| c11 | | Eugene Goldberg, Kanupriya Gulati: On Complexity of Internal and External Equivalence Checking. DSD 2007: 197-206 |
| c10 | | Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri: Toggle Equivalence Preserving (TEP) Logic Optimization. DSD 2007: 271-279 |
| c9 | | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A Structured ASIC Design Approach Using Pass Transistor Logic. ISCAS 2007: 1787-1790 |
| 2006 | ||
| c8 | | Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri: Controlling inductive cross-talk and power in off-chip buses using CODECs. ASP-DAC 2006: 850-855 |
| c7 | | Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri: A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222 |
| c6 | | Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson: Network coding for routability improvement in VLSI. ICCAD 2006: 820-823 |
| c5 | | Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi: An Efficient, Scalable Hardware Engine for Boolean SATisfiability. ICCD 2006 |
| c4 | | Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri: Memory-based crosstalk canceling CODECs for on-chip buses. ISCAS 2006 |
| c3 | | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: A probabilistic method to determine the minimum leakage vector for combinational designs. ISCAS 2006 |
| c2 | | Kanupriya Gulati, M. Lovell, Sunil P. Khatri: Efficient don't care computation for hierarchical designs. ISCAS 2006 |
| 2005 | ||
| c1 | | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri: An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. ISLPED 2005: 111-114 |
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