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 | 2006 | |
|---|---|---|
| j1 |      | H. C. Yeo, N. Guo, H. Du, W. M. Huang, X. M. Jian: Characterisation of IC packaging interfaces and loading effects. Microelectronics Reliability 46(9-11): 1892-1897 (2006) |
| 2001 | ||
| c1 | | D. Zhou, Wei Li, W. Cai, N. Guo: An efficient balanced truncation realization algorithm for interconnect model order reduction. ISCAS (5) 2001: 383-386 |
| 1 | W. Cai | |
| 2 | H. Du | |
| 3 | W. M. Huang | |
| 4 | X. M. Jian | |
| 5 | Wei Li | |
| 6 | H. C. Yeo | |
| 7 | D. Zhou |
Colors in the list of coauthors
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